perf/x86/intel/pt: Fix topa_entry base length
authorMarco Cavenati <cavenati.marco@gmail.com>
Mon, 24 Jun 2024 20:10:55 +0000 (23:10 +0300)
committerPeter Zijlstra <peterz@infradead.org>
Thu, 4 Jul 2024 14:00:20 +0000 (16:00 +0200)
commit5638bd722a44bbe97c1a7b3fae5b9efddb3e70ff
treeb3cc6465defd9430474b143824efc6b2871ab974
parentf8a86a9bb5f7e65d8c4405052de062639a8783bb
perf/x86/intel/pt: Fix topa_entry base length

topa_entry->base needs to store a pfn.  It obviously needs to be
large enough to store the largest possible x86 pfn which is
MAXPHYADDR-PAGE_SIZE (52-12).  So it is 4 bits too small.

Increase the size of topa_entry->base from 36 bits to 40 bits.

Note, systems where physical addresses can be 256TiB or more are affected.

[ Adrian: Amend commit message as suggested by Dave Hansen ]

Fixes: 52ca9ced3f70 ("perf/x86/intel/pt: Add Intel PT PMU driver")
Signed-off-by: Marco Cavenati <cavenati.marco@gmail.com>
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20240624201101.60186-2-adrian.hunter@intel.com
arch/x86/events/intel/pt.h