drm/amd/display: Support CW4 for DMUB ringbuffer inbox
authorNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Thu, 7 May 2020 17:35:41 +0000 (13:35 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 28 May 2020 18:00:48 +0000 (14:00 -0400)
commit562c805f83d251201abc776341fa3ba0521d3f13
tree8ff2f9ac82b04e3c589d162bb8e517e0ff58a555
parent455802c72faf7524e05295bde564728f10e94d1c
drm/amd/display: Support CW4 for DMUB ringbuffer inbox

[Why]
Region 4 is non cacheable and slower than using cache window 4.

[How]
Check the firmware version to determine how we should program the
base address and memory windows.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c