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(parent: 21822b6) | patch
drm/amdgpu: use cached ih rb control reg offsets for vega10
authorHawking Zhang <Hawking.Zhang@amd.com>
Tue, 1 Dec 2020 15:13:12 +0000 (23:13 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 23 Dec 2020 20:04:14 +0000 (15:04 -0500)
commit554bdbf6de74f5bd5852ce147c06172beb25a831
tree403701a97a11ba3c16510f547ac61639a7992d56tree
parent21822b6a968d948ae6cd09dfe7f4e43916d97b0ecommit | diff
drm/amdgpu: use cached ih rb control reg offsets for vega10

all the ih rb control register offsets are cached
at the beginning of ih_sw_init.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/vega10_ih.c diff | blob | history
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