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(parent: 2478e22) | patch
drm/i915/psr: Fix PSR sink enable sequence
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 11 Sep 2024 15:18:36 +0000 (18:18 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 18 Sep 2024 20:25:18 +0000 (23:25 +0300)
commit52c4abeec6fd40f492dead85beb2652719f479c3
tree61ab2af72b7aac0fd7708854af9d42cdb0c28bfctree
parent2478e2234d7d0196138fa2be3e5e538eae3ff888commit | diff
drm/i915/psr: Fix PSR sink enable sequence

According to the eDP spec, the source must first configure all
PSR related DPCD registers apart from the actual enable bit,
and only then set the enable bit. Split the current single DPCD
write to two to match the spec.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240911151836.16800-1-ville.syrjala@linux.intel.com
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
drivers/gpu/drm/i915/display/intel_psr.c diff | blob | history
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