drm/i915/icl: Get DDI clock for ICL based on PLLs.
authorManasi Navare <manasi.d.navare@intel.com>
Wed, 23 May 2018 22:44:44 +0000 (15:44 -0700)
committerPaulo Zanoni <paulo.r.zanoni@intel.com>
Fri, 1 Jun 2018 23:14:38 +0000 (16:14 -0700)
commit51c83cfaf96382ab65717d694f80af86482ba795
tree4eef84a067d74f440b9007052398f3758b56ff2c
parentf17ca5010c34e99e4035f22437f8b83452584a26
drm/i915/icl: Get DDI clock for ICL based on PLLs.

PLLs are the source clocks for the DDIs so in order
to determine the ddi clock we need to check the PLL
configuration.

This gets a little tricky for ICL since there is
no register bit that maps directly to the link clock.
So this patch creates a separate function in intel_dpll_mgr.c
to obtain the write array PLL Params and compares the set
pll_params with the table to get the corresponding link
clock.

v2:
  - Fix the encoder type check (DK).
  - Improve our error checking, return a sane value (Mika, Paulo).
  - Fix table entries (Paulo).

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
[Paulo: implement v2]
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180523224444.19017-1-paulo.r.zanoni@intel.com
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_ddi.c
drivers/gpu/drm/i915/intel_dpll_mgr.c
drivers/gpu/drm/i915/intel_dpll_mgr.h