pinctrl: sh-pfc: r8a7795: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D
authorTakeshi Kihara <takeshi.kihara.df@renesas.com>
Fri, 28 Jul 2017 11:41:13 +0000 (20:41 +0900)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 16 Aug 2017 12:26:24 +0000 (14:26 +0200)
commit50d83156e84ee5112fa07a0033eef4e58110709d
tree8ff1ad161f13baf2b60e6e5ec7080d6d7edb02e3
parent933ddbe5f52fbd6bdb03b976b7b1b80230b3b9a9
pinctrl: sh-pfc: r8a7795: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D

This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24]
value when STP_ISEN_1_D pin function is selected for IPSR17 bit[27:24].

This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7795 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.

Fixes: 0b0ffc96dbe30fa9 ("pinctrl: sh-pfc: Initial R8A7795 PFC support")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/pinctrl/sh-pfc/pfc-r8a7795.c