drm/i915/cnl: Add support slice/subslice/eu configs
authorBen Widawsky <ben@bwidawsk.net>
Wed, 20 Sep 2017 18:35:24 +0000 (11:35 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Tue, 26 Sep 2017 20:02:44 +0000 (13:02 -0700)
commit4e9767bc28e93139442847f023ff2fc0c2a21d34
tree9a5fd8afce32d9f6baae006b3321146763bfc890
parent4d34b11e46184bb5762491d32566fade188c6c01
drm/i915/cnl: Add support slice/subslice/eu configs

Cannonlake Slice and Subslice information has changed.

This patch initially provided by Ben adds the proper sseu
initialization.

v2: This v2 done by Rodrigo includes:
    - Fix on Total slices count by avoiding [1][2] and [2][2].
    - Inclusion of EU Per Subslice.
    - Commit message.
v3: This v3 done by Rodrigo includes:
    - Handle all possible bits and extra fuse register.
    - Use INTEL_GEN macro.
    - Fully assume uniform distribution so remove union
      with eu_per_subslice and add proper the comment.
v4: This v4 done by Rodrigo includes:
    - Consider all bits available: 6 bits for slices [27:22]
      and 4 for subslices [21:18].
v5: This v5 done by Rodrigo includes:
    - sseu->subslice_mask = (1 << 4) - 1 - missed on previous
    versions and noticed by Oscar.

Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170920183525.20530-1-rodrigo.vivi@intel.com
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_device_info.c