arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify inter...
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tue, 25 Oct 2022 22:06:28 +0000 (23:06 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 28 Oct 2022 12:22:59 +0000 (14:22 +0200)
commit49669da644cf000eb79dbede55bd04acf3f2f0a0
treebace807eb076056cf10450caa296d41e70d291bd
parent5b093eb67e36182f3bad4375c79278b7236d3bd7
arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property

Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property so
that we can share the common parts of the SoC DTSI with the RZ/Five
(RISC-V) SoC and the RZ/G2UL (ARM64) SoC.

This patch adds a new file r9a07g043u.dtsi to separate out RZ/G2UL
(ARM64) SoC specific parts.  No functional changes (same DTB).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221025220629.79321-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts