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PCI: cadence: Retrain Link to work around Gen2 training defect
authorNadeem Athani <nadeem@cadence.com>
Tue, 9 Feb 2021 14:46:21 +0000 (15:46 +0100)
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Wed, 10 Feb 2021 12:48:45 +0000 (12:48 +0000)
commit4740b969aaf58adeca6829947a3ad8da423976cf
tree1d1980fd69098195242074bab9e9313e15e12bb6tree | snapshot
parent7c53f6b671f4aba70ff15e1b05148b10d58c2837commit | diff
PCI: cadence: Retrain Link to work around Gen2 training defect

Cadence controller will not initiate autonomous speed change if strapped
as Gen2. The Retrain Link bit is set as quirk to enable this speed change.

Link: https://lore.kernel.org/r/20210209144622.26683-3-nadeem@cadence.com
Signed-off-by: Nadeem Athani <nadeem@cadence.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
drivers/pci/controller/cadence/pci-j721e.c diff | blob | history
drivers/pci/controller/cadence/pcie-cadence-host.c diff | blob | history
drivers/pci/controller/cadence/pcie-cadence.h diff | blob | history
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