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(parent: 1e40ef8) | patch
drm/amd/display: Add FRL registers for DCN30
authorRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Wed, 17 May 2023 00:40:20 +0000 (18:40 -0600)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 11 May 2026 20:15:03 +0000 (16:15 -0400)
commit4305b6e9705d1500fe7186aa27e764dc5d7b7871
tree8c543480cbeff12bd900ae22057fd87bef9d0e9ftree
parent1e40ef87ffdc291e05ccdade8b9170cc9c1c4249commit | diff
drm/amd/display: Add FRL registers for DCN30

Introduce the stream creation function, which requires the FRL
registers for DCN30.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h diff | blob | history
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h diff | blob | history
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