arch_topology: Add support to parse and detect cache attributes
authorSudeep Holla <sudeep.holla@arm.com>
Mon, 4 Jul 2022 10:15:53 +0000 (11:15 +0100)
committerSudeep Holla <sudeep.holla@arm.com>
Mon, 4 Jul 2022 15:22:28 +0000 (16:22 +0100)
commit38db9b95464f82fed28794afe0214d9439d86f7c
tree7c9832e04afeeb5b21fce2d7da89809c8ef9eb93
parent521103134a0d07774c8b17f25ff0ef70cbd56c9d
arch_topology: Add support to parse and detect cache attributes

Currently ACPI populates just the minimum information about the last
level cache from PPTT in order to feed the same to build sched_domains.
Similar support for DT platforms is not present.

In order to enable the same, the entire cache hierarchy information can
be built as part of CPU topoplogy parsing both on ACPI and DT platforms.

Note that this change builds the cacheinfo early even on ACPI systems,
but the current mechanism of building llc_sibling mask remains unchanged.

Link: https://lore.kernel.org/r/20220704101605.1318280-10-sudeep.holla@arm.com
Tested-by: Ionela Voinescu <ionela.voinescu@arm.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
drivers/base/arch_topology.c