net/mlx5: Bridge, support pvid and untagged vlan configurations
authorVlad Buslov <vladbu@nvidia.com>
Fri, 2 Apr 2021 12:09:06 +0000 (15:09 +0300)
committerSaeed Mahameed <saeedm@nvidia.com>
Thu, 10 Jun 2021 01:36:11 +0000 (18:36 -0700)
commit36e55079e54955a70b2c340eedd6125f794a911d
tree4ca2a84ea679be07a3cb571e0743dc43f4ee969f
parentffc89ee5e5e88aa5924034c28d5e5aae75229e0f
net/mlx5: Bridge, support pvid and untagged vlan configurations

Implement support for pushing vlan header into untagged packet on ingress
of port that has pvid configured and support for popping vlan on egress of
port that has the matching vlan configured as untagged. To support such
configurations packet reformat contexts of {INSERT|REMOVE}_HEADER types are
created per such vlan and saved to struct mlx5_esw_bridge_vlan which allows
all FDB entries on particular vlan to share single packet reformat
instance. When initializing FDB entries with pvid or untagged vlan type set
its mlx5_flow_act->pkt_reformat action accordingly.

Flush all flows when removing vlan from port. This is necessary because
even though software bridge removes all FDB entries before removing their
vlan, mlx5 bridge implementation deletes their corresponding flow entries
from hardware in asynchronous workqueue task, which will cause firmware
error if vlan packet reformat context is deleted before all flows that
point to it.

Signed-off-by: Vlad Buslov <vladbu@nvidia.com>
Reviewed-by: Jianbo Liu <jianbol@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Documentation/networking/device_drivers/ethernet/mellanox/mlx5.rst
drivers/net/ethernet/mellanox/mlx5/core/esw/bridge.c