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(parent: 5bad9d8) | patch
drm/amd/display: Introduce FRL registers for DCN32
authorRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Thu, 18 May 2023 20:43:39 +0000 (14:43 -0600)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 11 May 2026 20:15:13 +0000 (16:15 -0400)
commit332b9fe92cdd1251a94c560870dad96ee319b368
treead00362da4939dace64a45c7c4ad27925b57ca0dtree
parent5bad9d8a1e70667be030dceb06257f472407777acommit | diff
drm/amd/display: Introduce FRL registers for DCN32

This commit add the basic set of FRL registers associated with DCN32.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h diff | blob | history
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h diff | blob | history
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