perf/x86/intel: Add event constraint for CYCLE_ACTIVITY.STALLS_MEM_ANY
authorKan Liang <kan.liang@linux.intel.com>
Mon, 19 Oct 2020 16:45:29 +0000 (09:45 -0700)
committerPeter Zijlstra <peterz@infradead.org>
Thu, 29 Oct 2020 10:00:41 +0000 (11:00 +0100)
commit306e3e91edf1c6739a55312edd110d298ff498dd
treeb0b93898337d85d00c3b862b0c7c232b84610c04
parent43bc103a8044b9f7963aa1684efbdc9bd60939de
perf/x86/intel: Add event constraint for CYCLE_ACTIVITY.STALLS_MEM_ANY

The event CYCLE_ACTIVITY.STALLS_MEM_ANY (0x14a3) should be available on
all 8 GP counters on ICL, but it's only scheduled on the first four
counters due to the current ICL constraint table.

Add a line for the CYCLE_ACTIVITY.STALLS_MEM_ANY event in the ICL
constraint table.
Correct the comments for the CYCLE_ACTIVITY.CYCLES_MEM_ANY event.

Fixes: 6017608936c1 ("perf/x86/intel: Add Icelake support")
Reported-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20201019164529.32154-1-kan.liang@linux.intel.com
arch/x86/events/intel/core.c