projects / linux-2.6-microblaze.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: ed9feec) | patch
mmc: sunxi: Support MMC_DDR52 timing modes
authorChen-Yu Tsai <wens@csie.org>
Fri, 29 Jan 2016 17:21:46 +0000 (01:21 +0800)
committerUlf Hansson <ulf.hansson@linaro.org>
Mon, 29 Feb 2016 10:02:57 +0000 (11:02 +0100)
commit2dcb305a9ef0f98645dafa6d916936772fde2ad5
tree88185fb5ddc9d6eb25709ea7927928fbd64a107btree
parented9feec72fc1fa194ebfdb79e14561b35decce63commit | diff
mmc: sunxi: Support MMC_DDR52 timing modes

DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52).
Consider MMC_DDR52 when setting clock delays.

Since MMC high speed mode goes up to 52 MHz instead of 50 MHz for SD,
and this number is visible in the capability macro, increase the
clock rate upper limit to 52 MHz.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
drivers/mmc/host/sunxi-mmc.c diff | blob | history
MicroBlaze GIT Repository