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RISC-V: defconfig: Enable RISC-V SBI earlycon support
authorAnup Patel <anup@brainfault.org>
Tue, 4 Dec 2018 13:55:06 +0000 (19:25 +0530)
committerPalmer Dabbelt <palmer@sifive.com>
Mon, 17 Dec 2018 18:23:46 +0000 (10:23 -0800)
commit2b3f786408c5400705ed722ab2f3065e86272857
tree7759dcc86df915965c70b608b547a768b6a2257atree | snapshot
parent7566ec393f4161572ba6f11ad5171fd5d59b0fbdcommit | diff
RISC-V: defconfig: Enable RISC-V SBI earlycon support

This patch enables RISC-V SBI earlycon support in default defconfig
so that we can use "earlycon=sbi" in kernel parameters for early
debug prints.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
arch/riscv/configs/defconfig diff | blob | history
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