ptp: add FemtoClock3 Wireless as ptp hardware clock
authorMin Li <min.li.xe@renesas.com>
Wed, 24 Jan 2024 18:49:47 +0000 (13:49 -0500)
committerDavid S. Miller <davem@davemloft.net>
Mon, 29 Jan 2024 13:00:23 +0000 (13:00 +0000)
commit1ddfecafabf71e0e5345dff877d2680083c7e078
tree842dc747c1f3c361055f346b4c226e55862080bb
parentea1cc3ee34a5f3144f6c2cdc07c19c914ccb9526
ptp: add FemtoClock3 Wireless as ptp hardware clock

The RENESAS FemtoClock3 Wireless is a high-performance jitter attenuator,
frequency translator, and clock synthesizer. The device is comprised of 3
digital PLLs (DPLL) to track CLKIN inputs and three independent low phase
noise fractional output dividers (FOD) that output low phase noise clocks.

FemtoClock3 supports one Time Synchronization (Time Sync) channel to enable
an external processor to control the phase and frequency of the Time Sync
channel and to take phase measurements using the TDC. Intended applications
are synchronization using the precision time protocol (PTP) and
synchronization with 0.5 Hz and 1 Hz signals from GNSS.

Signed-off-by: Min Li <min.li.xe@renesas.com>
Acked-by: Lee Jones <lee@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/ptp/Kconfig
drivers/ptp/Makefile
drivers/ptp/ptp_fc3.c [new file with mode: 0644]
drivers/ptp/ptp_fc3.h [new file with mode: 0644]
include/linux/mfd/idtRC38xxx_reg.h [new file with mode: 0644]