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author	Michael Strauss <michael.strauss@amd.com>
	Thu, 9 Jun 2022 14:45:34 +0000 (10:45 -0400)
committer	Alex Deucher <alexander.deucher@amd.com>
	Mon, 25 Jul 2022 21:16:45 +0000 (17:16 -0400)
commit	1c5a2fa97b91d37375f4fc8aeb37c9456c93c828
tree	61fd64e7e004bb9ba3467e79bbb7a3261d5d9431	tree
parent	cb849b4dc73d414149fea96330cdf96a82919fc9	commit \| diff

drm/amd/display: Use correct DTO_SRC_SEL for 128b/132b encoding

[WHY]
DP DTO isn't used for 128b/132b encoding

[HOW]
Check current link rate to determine whether using 8b/10b or 128/132b encoding

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

MicroBlaze GIT Repository

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drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c		diff \| blob \| history
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c		diff \| blob \| history
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c		diff \| blob \| history
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c		diff \| blob \| history
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c		diff \| blob \| history
drivers/gpu/drm/amd/display/dc/inc/clock_source.h		diff \| blob \| history