ARM: dts: am4372: Add the PRU-ICSS1 DT node

ARM: dts: am4372: Add the PRU-ICSS1 DT node

Add the DT node for the PRU-ICSS1 instance on the AM437x family of SoCs.
Each PRU-ICSS instance is represented by a pruss node and other child
nodes. The nodes are added under the interconnect target module node in
the common am4372 dtsi file. The PRU-ICSS instances are supported only
on AM4376+ SoCs though in the AM437x family, so the interconnect target
module node should be disabled in any derivative board dts file that
uses AM4372 SoCs.

The PRU-ICSS1 on AM437x is very similar to the PRUSS in AM33xx, except
for variations in the RAM sizes, bus addresses and the number of
interrupts coming into the MPU INTC (host interrupt 5 is routed to
the other PRUSS instead of MPU).

The PRUSS subsystem node contains the entire address space. The various
sub-modules of the PRU-ICSS are represented as individual child nodes
(so platform devices themselves) of the PRUSS subsystem node. These
include the two PRU cores and the interrupt controller. All the Data
RAMs are represented within a child node of its own named 'memories'
without any compatible. The Real Time Media Independent Interface
controller (MII_RT), and the CFG sub-module are represented as syscon
nodes. The PRUSS CFG module has a clock mux for IEP clock, this clk
node is added under the CFG child node 'clocks'. The default source
for this mux clock is the PRU_ICSS_IEP_GCLK clock.

The DT nodes use all standard properties. The regs property in the PRU
nodes define the addresses for the Instruction RAM, the Debug and Control
sub-modules for that PRU core. The firmware for each PRU core is defined
through a 'firmware-name' property.

The default names for the firmware images for each PRU core are defined
as follows (these can be adjusted either in derivative board dts files
or through sysfs at runtime if required):
     PRU-ICSS1 PRU0 Core: am437x-pru1_0-fw
     PRU-ICSS1 PRU1 Core: am437x-pru1_1-fw

Note:
1. There are few more sub-modules like the Industrial Ethernet Peripheral
   (IEP), MDIO, UART, eCAP that do not have bindings and so will be added
   in the future.
2. The PRUSS INTC on AM437x SoCs also connect the host interrupt 0 to ADC0
   and ADC1; 6 and 7 as possible DMA events, so use the 'ti,irqs-reserved'
   property in derivative board dts files _if_ any of them should not be
   handled by the host OS. Host interrupt 5 is already marked reserved as
   it is connected to the other PRUSS instance.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>