drm/xe: Clarify register types on PAT programming
authorLucas De Marchi <lucas.demarchi@intel.com>
Thu, 27 Apr 2023 22:32:50 +0000 (15:32 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Tue, 19 Dec 2023 23:32:21 +0000 (18:32 -0500)
commit143e3bc7832f85676d0e4235d4238f0c9b0682da
tree8deb88410d5aa0a244c90048696c21a80c551136
parent5f230a144a33d9a33448063a23d65c53b6d84cea
drm/xe: Clarify register types on PAT programming

Clarify a few things related to the PAT programming, particularly on
MTL:

- The register type doesn't change depending on the GT - what
  happens is that media GT writes to other set of registers that
  are not MCR
- Remove "UNICAST": otherwise it's confusing why it's not using
  MCR registers with the unicast function variant

Also, there isn't much reason to keep those parts as macros: promote
them to proper functions and let the compiler inline if it sees fit.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230427223256.1432787-5-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/xe/xe_pat.c