net/mlx5e: Fix macsec sci endianness at rx sa update
authorRaed Salem <raeds@nvidia.com>
Wed, 26 Oct 2022 13:51:53 +0000 (14:51 +0100)
committerJakub Kicinski <kuba@kernel.org>
Thu, 27 Oct 2022 18:06:57 +0000 (11:06 -0700)
commit12ba40ba3dc3a28ad579b7de2202ab6419da304a
treed72a28c86dd624b12977eb6f843a8556c3b2a550
parentd550956458a83cf87cb8fe24862f3340065c62c1
net/mlx5e: Fix macsec sci endianness at rx sa update

The cited commit at rx sa update operation passes the sci object
attribute, in the wrong endianness and not as expected by the HW
effectively create malformed hw sa context in case of update rx sa
consequently, HW produces unexpected MACsec packets which uses this
sa.

Fix by passing sci to create macsec object with the correct endianness,
while at it add __force u64 to prevent sparse check error of type
"sparse: error: incorrect type in assignment".

Fixes: aae3454e4d4c ("net/mlx5e: Add MACsec offload Rx command support")
Signed-off-by: Raed Salem <raeds@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Link: https://lore.kernel.org/r/20221026135153.154807-16-saeed@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c