clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset
authorSimon Horman <horms+renesas@verge.net.au>
Mon, 25 Mar 2019 16:35:51 +0000 (17:35 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 2 Apr 2019 07:50:48 +0000 (09:50 +0200)
commit10d9ea5100c89afd677a202036e0e34e129a6c52
tree8d2e6c4f2701568ac3b13048556dc89989a4be26
parent20cc05ba04a93f05d6c50789fe35d762a2db4e96
clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset

Parameterise the offset of control bits within the FRQCRC register
for Z and Z2 clocks.

This is in preparation for supporting the Z2 clock on the R-Car E3
(r8a77990) SoC which uses a different offset for control bits to
other, already, supported SoCs.

As suggested by Geert Uytterhoeven.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r8a774a1-cpg-mssr.c
drivers/clk/renesas/r8a7795-cpg-mssr.c
drivers/clk/renesas/r8a7796-cpg-mssr.c
drivers/clk/renesas/r8a77965-cpg-mssr.c
drivers/clk/renesas/rcar-gen3-cpg.c
drivers/clk/renesas/rcar-gen3-cpg.h