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(parent: c57cae7) | patch
cxl/core/port: Rename bus.c to port.c
authorDan Williams <dan.j.williams@intel.com>
Mon, 24 Jan 2022 00:29:21 +0000 (16:29 -0800)
committerDan Williams <dan.j.williams@intel.com>
Wed, 9 Feb 2022 06:57:28 +0000 (22:57 -0800)
commit0ff0af18216436d0151af4e410400c7a19ca9437
treeb4982719f3e547332a73664764d0318ea4011892tree | snapshot
parentc57cae78bfa6a8535d4baade451107b0577c2750commit | diff
cxl/core/port: Rename bus.c to port.c

Given it is dominated by port infrastructure, and will only acquire
more, rename bus.c to port.c.

Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Link: https://lore.kernel.org/r/164298416136.3018233.15442880970000855425.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Documentation/driver-api/cxl/memory-devices.rst diff | blob | history
drivers/cxl/core/Makefile diff | blob | history
drivers/cxl/core/bus.c [deleted file] blob | history
drivers/cxl/core/port.c [new file with mode: 0644] blob
tools/testing/cxl/Kbuild diff | blob | history
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