drm: rcar-du: Fix DU3 start/stop on M3-N
authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Fri, 23 Nov 2018 11:38:17 +0000 (13:38 +0200)
committerLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Mon, 26 Nov 2018 08:42:22 +0000 (10:42 +0200)
commit0bc3544a010c1e460c99fa052991789f113d860e
treecf1581e6f79c8263e0adffce1d8f36e25fc8d29e
parent2e6e902d185027f8e3cb8b7305238f7e35d6a436
drm: rcar-du: Fix DU3 start/stop on M3-N

Group start/stop is controlled by the DRES and DEN bits of DSYSR0 for
the first group and DSYSR2 for the second group. On most DU instances,
this maps to the first CRTC of the group. On M3-N, however, DU2 doesn't
exist, but DSYSR2 does. There is no CRTC object there that maps to the
correct DSYSR register.

Commit 9144adc5e5a9 ("drm: rcar-du: Cache DSYSR value to ensure known
initial value") switched group start/stop from using group read/write
access to DSYSR to a CRTC-based API to cache the DSYSR value. While
doing so, it introduced a regression on M3-N by accessing DSYSR3 instead
of DSYSR2 to start/stop the second group.

To fix this, access the DSYSR register directly through group read/write
if the SoC is missing the first DU channel of the group. Keep using the
rcar_du_crtc_dsysr_clr_set() function otherwise, to retain the DSYSR
caching feature.

Fixes: 9144adc5e5a9 ("drm: rcar-du: Cache DSYSR value to ensure known initial value")
Reported-by: Hoan Nguyen An <na-hoan@jinso.co.jp>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
drivers/gpu/drm/rcar-du/rcar_du_group.c