drm/i915/gen9: fix the WaWmMemoryReadLatency implementation
authorPaulo Zanoni <paulo.r.zanoni@intel.com>
Thu, 22 Sep 2016 21:00:30 +0000 (18:00 -0300)
committerPaulo Zanoni <paulo.r.zanoni@intel.com>
Mon, 26 Sep 2016 19:51:43 +0000 (16:51 -0300)
commit0727e40a48a1d08cf54ce2c01e120864b92e59bf
treebce587b40451fdf42f153390cfb52b7df4781cf8
parent6e3100ec21e7c774a0fc01e36a1e0739530c2f71
drm/i915/gen9: fix the WaWmMemoryReadLatency implementation

Bspec says:
  "The mailbox response data may not account for memory read latency.
   If the mailbox response data for level 0 is 0us, add 2 microseconds
   to the result for each valid level."

This means we should only do the +2 in case wm[0] == 0, not always.

So split the sanitizing implementation from the WA implementation and
fix the WA implementation.

v2: Add Fixes tag (Maarten).

Fixes: 367294be7c25 ("drm/i915/gen9: Add 2us read latency to WM level")
Cc: stable@vger.kernel.org
Cc: Vandana Kannan <vandana.kannan@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1474578035-424-5-git-send-email-paulo.r.zanoni@intel.com
drivers/gpu/drm/i915/intel_pm.c