drm/i915: Read C0DRB3/C1DRB3 as 16 bits again
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 21 Apr 2021 15:33:59 +0000 (18:33 +0300)
committerJani Nikula <jani.nikula@intel.com>
Wed, 12 May 2021 17:52:32 +0000 (20:52 +0300)
commit04d019961fd15de92874575536310243a0d4c5c5
tree4a9af5b54e446b4a8077bbadb79356d1d8d931b3
parent4819d16d91145966ce03818a95169df1fd56b299
drm/i915: Read C0DRB3/C1DRB3 as 16 bits again

We've defined C0DRB3/C1DRB3 as 16 bit registers, so access them
as such.

Fixes: 1c8242c3a4b2 ("drm/i915: Use unchecked writes for setting up the fences")
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210421153401.13847-3-ville.syrjala@linux.intel.com
(cherry picked from commit f765a5b48c667bdada5e49d5e0f23f8c0687b21b)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c