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clk: renesas: rzg2l: Add support for RZ/G3S PLL
authorClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Fri, 29 Sep 2023 05:38:54 +0000 (08:38 +0300)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 5 Oct 2023 11:45:22 +0000 (13:45 +0200)
commit01eabef547e63d80086acd3f247d36c5f9f92456
tree4e1a3ace3cf93fa0e9bb7c6f13ff04f0b32d00e4tree | snapshot
parent5f710e3bc5987373737470f98798bbd49134a2e0commit | diff
clk: renesas: rzg2l: Add support for RZ/G3S PLL

Add support for reading the frequency of PLL1/4/6 as available on
RZ/G3S.  The computation formula for the PLL frequency is as follows:

    Fout = (nir + nfr / 4096) * Fin / (mr * pr)

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-8-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/rzg2l-cpg.c diff | blob | history
drivers/clk/renesas/rzg2l-cpg.h diff | blob | history
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