X-Git-Url: http://git.monstr.eu/?a=blobdiff_plain;f=tools%2Fperf%2Fpmu-events%2Farch%2Fx86%2Famdzen2%2Fcache.json;h=f61b982f83ca3d9139ce198be58396517a82a908;hb=08ed77e414ab234258166f5628d91a7a0e681ff4;hp=1c60bfa0f00b93944f033a09ac0a17006834f571;hpb=c45e8bccecaf633480d378daff11e122dfd5e96d;p=linux-2.6-microblaze.git

diff --git a/tools/perf/pmu-events/arch/x86/amdzen2/cache.json b/tools/perf/pmu-events/arch/x86/amdzen2/cache.json
index 1c60bfa0f00b..f61b982f83ca 100644
--- a/tools/perf/pmu-events/arch/x86/amdzen2/cache.json
+++ b/tools/perf/pmu-events/arch/x86/amdzen2/cache.json
@@ -47,6 +47,11 @@
     "BriefDescription": "Miscellaneous events covered in more detail by l2_request_g2 (PMCx061).",
     "UMask": "0x1"
   },
+  {
+    "EventName": "l2_request_g1.all_no_prefetch",
+    "EventCode": "0x60",
+    "UMask": "0xf9"
+  },
   {
     "EventName": "l2_request_g2.group1",
     "EventCode": "0x61",
@@ -173,6 +178,24 @@
     "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2.",
     "UMask": "0x1"
   },
+  {
+    "EventName": "l2_cache_req_stat.ic_access_in_l2",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache requests in L2.",
+    "UMask": "0x7"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ic_dc_miss_in_l2",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 and Data cache request miss in L2 (all types).",
+    "UMask": "0x9"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ic_dc_hit_in_l2",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in L2 (all types).",
+    "UMask": "0xf6"
+  },
   {
     "EventName": "l2_fill_pending.l2_fill_busy",
     "EventCode": "0x6d",