X-Git-Url: http://git.monstr.eu/?a=blobdiff_plain;ds=sidebyside;f=Documentation%2Fvm%2Fmmu_notifier.rst;h=df5d7777fc6b53c49bb2d6b7bf16b51c5d110235;hb=15b447361794271f4d03c04d82276a841fe06328;hp=47baa1cf28c572eb58d6506500a415646e205798;hpb=b72f711a4efadfaa8a16f9cb708bfe1ce6125906;p=linux-2.6-microblaze.git

diff --git a/Documentation/vm/mmu_notifier.rst b/Documentation/vm/mmu_notifier.rst
index 47baa1cf28c5..df5d7777fc6b 100644
--- a/Documentation/vm/mmu_notifier.rst
+++ b/Documentation/vm/mmu_notifier.rst
@@ -89,7 +89,7 @@ they are write protected for COW (other case of B apply too).
 
 So here because at time N+2 the clear page table entry was not pair with a
 notification to invalidate the secondary TLB, the device see the new value for
-addrB before seing the new value for addrA. This break total memory ordering
+addrB before seeing the new value for addrA. This break total memory ordering
 for the device.
 
 When changing a pte to write protect or to point to a new write protected page