riscv: andes: Support specifying symbolic firmware and hardware raw events

[linux-2.6-microblaze.git] / tools / perf / pmu-events / arch / riscv / andes / ax45 / memory.json

diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
new file mode 100644 (file)
index 0000000..c7401b5
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
@@ -0,0 +1,57 @@
+[
+       {
+               "EventCode": "0x01",
+               "EventName": "ilm_access",
+               "BriefDescription": "ILM access"
+       },
+       {
+               "EventCode": "0x11",
+               "EventName": "dlm_access",
+               "BriefDescription": "DLM access"
+       },
+       {
+               "EventCode": "0x21",
+               "EventName": "icache_access",
+               "BriefDescription": "ICACHE access"
+       },
+       {
+               "EventCode": "0x31",
+               "EventName": "icache_miss",
+               "BriefDescription": "ICACHE miss"
+       },
+       {
+               "EventCode": "0x41",
+               "EventName": "dcache_access",
+               "BriefDescription": "DCACHE access"
+       },
+       {
+               "EventCode": "0x51",
+               "EventName": "dcache_miss",
+               "BriefDescription": "DCACHE miss"
+       },
+       {
+               "EventCode": "0x61",
+               "EventName": "dcache_load_access",
+               "BriefDescription": "DCACHE load access"
+       },
+       {
+               "EventCode": "0x71",
+               "EventName": "dcache_load_miss",
+               "BriefDescription": "DCACHE load miss"
+       },
+       {
+               "EventCode": "0x81",
+               "EventName": "dcache_store_access",
+               "BriefDescription": "DCACHE store access"
+       },
+       {
+               "EventCode": "0x91",
+               "EventName": "dcache_store_miss",
+               "BriefDescription": "DCACHE store miss"
+       },
+       {
+               "EventCode": "0xA1",
+               "EventName": "dcache_wb",
+               "BriefDescription": "DCACHE writeback"
+       }
+]