ASoC: fsl_sai: Set SAI Channel Mode to Output Mode

[linux-2.6-microblaze.git] / sound / soc / fsl / fsl_sai.c

diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 38c7bcb..b2d65e5 100644 (file)
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -489,6 +489,10 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
 
        val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
 
+       /* Set to output mode to avoid tri-stated data pins */
+       if (tx)
+               val_cr4 |= FSL_SAI_CR4_CHMOD;
+
        /*
         * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
         * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
@@ -497,7 +501,8 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
 
        if (!sai->is_slave_mode && fsl_sai_dir_is_synced(sai, adir)) {
                regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),
-                                  FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
+                                  FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
+                                  FSL_SAI_CR4_CHMOD_MASK,
                                   val_cr4);
                regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),
                                   FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
@@ -508,7 +513,8 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
                           FSL_SAI_CR3_TRCE_MASK,
                           FSL_SAI_CR3_TRCE((1 << pins) - 1));
        regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
-                          FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
+                          FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
+                          FSL_SAI_CR4_CHMOD_MASK,
                           val_cr4);
        regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
                           FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |