drm/xe: Move engine base offsets to engine register header
[linux-2.6-microblaze.git] / kernel / panic.c
index ffa037f..2807639 100644 (file)
@@ -192,14 +192,15 @@ atomic_t panic_cpu = ATOMIC_INIT(PANIC_CPU_INVALID);
  */
 void nmi_panic(struct pt_regs *regs, const char *msg)
 {
-       int old_cpu, cpu;
+       int old_cpu, this_cpu;
 
-       cpu = raw_smp_processor_id();
-       old_cpu = atomic_cmpxchg(&panic_cpu, PANIC_CPU_INVALID, cpu);
+       old_cpu = PANIC_CPU_INVALID;
+       this_cpu = raw_smp_processor_id();
 
-       if (old_cpu == PANIC_CPU_INVALID)
+       /* atomic_try_cmpxchg updates old_cpu on failure */
+       if (atomic_try_cmpxchg(&panic_cpu, &old_cpu, this_cpu))
                panic("%s", msg);
-       else if (old_cpu != cpu)
+       else if (old_cpu != this_cpu)
                nmi_panic_self_stop(regs);
 }
 EXPORT_SYMBOL(nmi_panic);
@@ -311,15 +312,18 @@ void panic(const char *fmt, ...)
         * stop themself or will wait until they are stopped by the 1st CPU
         * with smp_send_stop().
         *
-        * `old_cpu == PANIC_CPU_INVALID' means this is the 1st CPU which
-        * comes here, so go ahead.
+        * cmpxchg success means this is the 1st CPU which comes here,
+        * so go ahead.
         * `old_cpu == this_cpu' means we came from nmi_panic() which sets
         * panic_cpu to this CPU.  In this case, this is also the 1st CPU.
         */
+       old_cpu = PANIC_CPU_INVALID;
        this_cpu = raw_smp_processor_id();
-       old_cpu  = atomic_cmpxchg(&panic_cpu, PANIC_CPU_INVALID, this_cpu);
 
-       if (old_cpu != PANIC_CPU_INVALID && old_cpu != this_cpu)
+       /* atomic_try_cmpxchg updates old_cpu on failure */
+       if (atomic_try_cmpxchg(&panic_cpu, &old_cpu, this_cpu)) {
+               /* go ahead */
+       } else if (old_cpu != this_cpu)
                panic_smp_self_stop();
 
        console_verbose();