#define __CS35L41_H
#include <linux/regmap.h>
+#include <linux/firmware/cirrus/cs_dsp.h>
#define CS35L41_FIRSTREG 0x00000000
#define CS35L41_LASTREG 0x03804FE8
#define CS35L41_MAX_CACHE_REG 36
#define CS35L41_OTP_SIZE_WORDS 32
-#define CS35L41_VALID_PDATA 0x80000000
#define CS35L41_NUM_SUPPLIES 2
#define CS35L41_SCLK_MSTR_MASK 0x10
#define CS35L41_GLOBAL_EN_SHIFT 0
#define CS35L41_BST_EN_MASK 0x0030
#define CS35L41_BST_EN_SHIFT 4
+#define CS35L41_BST_DIS_FET_OFF 0x00
#define CS35L41_BST_EN_DEFAULT 0x2
#define CS35L41_AMP_EN_SHIFT 0
#define CS35L41_AMP_EN_MASK 1
#define CS35L41_TEMP_WARN_ERR_RLS 0x20
#define CS35L41_TEMP_ERR_RLS 0x40
+#define CS35L41_AMP_SHORT_ERR_RLS_SHIFT 1
+#define CS35L41_BST_SHORT_ERR_RLS_SHIFT 2
+#define CS35L41_BST_OVP_ERR_RLS_SHIFT 3
+#define CS35L41_BST_UVP_ERR_RLS_SHIFT 4
+#define CS35L41_TEMP_WARN_ERR_RLS_SHIFT 5
+#define CS35L41_TEMP_ERR_RLS_SHIFT 6
+
#define CS35L41_INT1_MASK_DEFAULT 0x7FFCFE3F
#define CS35L41_INT1_UNMASK_PUP 0xFEFFFFFF
#define CS35L41_INT1_UNMASK_PDN 0xFF7FFFFF
#define CS35L41_GPIO1_CTRL_SHIFT 16
#define CS35L41_GPIO2_CTRL_MASK 0x07000000
#define CS35L41_GPIO2_CTRL_SHIFT 24
-#define CS35L41_GPIO_CTRL_OPEN_INT 2
-#define CS35L41_GPIO_CTRL_ACTV_LO 4
-#define CS35L41_GPIO_CTRL_ACTV_HI 5
+#define CS35L41_GPIO_LVL_SHIFT 15
+#define CS35L41_GPIO_LVL_MASK BIT(CS35L41_GPIO_LVL_SHIFT)
#define CS35L41_GPIO_POL_MASK 0x1000
#define CS35L41_GPIO_POL_SHIFT 12
#define CS35L41_SPI_MAX_FREQ 4000000
#define CS35L41_REGSTRIDE 4
+enum cs35l41_boost_type {
+ CS35L41_INT_BOOST,
+ CS35L41_EXT_BOOST,
+ CS35L41_EXT_BOOST_NO_VSPK_SWITCH,
+};
+
enum cs35l41_clk_ids {
CS35L41_CLKID_SCLK = 0,
CS35L41_CLKID_LRCLK = 1,
CS35L41_CLKID_MCLK = 4,
};
-struct cs35l41_irq_cfg {
- bool irq_pol_inv;
- bool irq_out_en;
- int irq_src_sel;
+enum cs35l41_gpio1_func {
+ CS35L41_GPIO1_HIZ,
+ CS35L41_GPIO1_GPIO,
+ CS35L41_GPIO1_MDSYNC,
+ CS35L41_GPIO1_MCLK,
+ CS35L41_GPIO1_PDM_CLK,
+ CS35L41_GPIO1_PDM_DATA,
+};
+
+enum cs35l41_gpio2_func {
+ CS35L41_GPIO2_HIZ,
+ CS35L41_GPIO2_GPIO,
+ CS35L41_GPIO2_INT_OPEN_DRAIN,
+ CS35L41_GPIO2_MCLK,
+ CS35L41_GPIO2_INT_PUSH_PULL_LOW,
+ CS35L41_GPIO2_INT_PUSH_PULL_HIGH,
+ CS35L41_GPIO2_PDM_CLK,
+ CS35L41_GPIO2_PDM_DATA,
};
-struct cs35l41_platform_data {
+struct cs35l41_gpio_cfg {
+ bool valid;
+ bool pol_inv;
+ bool out_en;
+ unsigned int func;
+};
+
+struct cs35l41_hw_cfg {
+ bool valid;
int bst_ind;
int bst_ipk;
int bst_cap;
int dout_hiz;
- struct cs35l41_irq_cfg irq_config1;
- struct cs35l41_irq_cfg irq_config2;
+ struct cs35l41_gpio_cfg gpio1;
+ struct cs35l41_gpio_cfg gpio2;
+ unsigned int spk_pos;
+
+ enum cs35l41_boost_type bst_type;
};
struct cs35l41_otp_packed_element_t {
u32 word_offset;
};
+enum cs35l41_cspl_mbox_status {
+ CSPL_MBOX_STS_RUNNING = 0,
+ CSPL_MBOX_STS_PAUSED = 1,
+ CSPL_MBOX_STS_RDY_FOR_REINIT = 2,
+};
+
+enum cs35l41_cspl_mbox_cmd {
+ CSPL_MBOX_CMD_NONE = 0,
+ CSPL_MBOX_CMD_PAUSE = 1,
+ CSPL_MBOX_CMD_RESUME = 2,
+ CSPL_MBOX_CMD_REINIT = 3,
+ CSPL_MBOX_CMD_STOP_PRE_REINIT = 4,
+ CSPL_MBOX_CMD_HIBERNATE = 5,
+ CSPL_MBOX_CMD_OUT_OF_HIBERNATE = 6,
+ CSPL_MBOX_CMD_UNKNOWN_CMD = -1,
+ CSPL_MBOX_CMD_INVALID_SEQUENCE = -2,
+};
+
+/*
+ * IRQs
+ */
+#define CS35L41_IRQ(_irq, _name, _hand) \
+ { \
+ .irq = CS35L41_ ## _irq ## _IRQ,\
+ .name = _name, \
+ .handler = _hand, \
+ }
+
+struct cs35l41_irq {
+ int irq;
+ const char *name;
+ irqreturn_t (*handler)(int irq, void *data);
+};
+
+#define CS35L41_REG_IRQ(_reg, _irq) \
+ [CS35L41_ ## _irq ## _IRQ] = { \
+ .reg_offset = (CS35L41_ ## _reg) - CS35L41_IRQ1_STATUS1,\
+ .mask = CS35L41_ ## _irq ## _MASK \
+ }
+
+/* (0x0000E010) CS35L41_IRQ1_STATUS1 */
+#define CS35L41_BST_OVP_ERR_SHIFT 6
+#define CS35L41_BST_OVP_ERR_MASK BIT(CS35L41_BST_OVP_ERR_SHIFT)
+#define CS35L41_BST_DCM_UVP_ERR_SHIFT 7
+#define CS35L41_BST_DCM_UVP_ERR_MASK BIT(CS35L41_BST_DCM_UVP_ERR_SHIFT)
+#define CS35L41_BST_SHORT_ERR_SHIFT 8
+#define CS35L41_BST_SHORT_ERR_MASK BIT(CS35L41_BST_SHORT_ERR_SHIFT)
+#define CS35L41_TEMP_WARN_SHIFT 15
+#define CS35L41_TEMP_WARN_MASK BIT(CS35L41_TEMP_WARN_SHIFT)
+#define CS35L41_TEMP_ERR_SHIFT 17
+#define CS35L41_TEMP_ERR_MASK BIT(CS35L41_TEMP_ERR_SHIFT)
+#define CS35L41_AMP_SHORT_ERR_SHIFT 31
+#define CS35L41_AMP_SHORT_ERR_MASK BIT(CS35L41_AMP_SHORT_ERR_SHIFT)
+
+enum cs35l41_irq_list {
+ CS35L41_BST_OVP_ERR_IRQ,
+ CS35L41_BST_DCM_UVP_ERR_IRQ,
+ CS35L41_BST_SHORT_ERR_IRQ,
+ CS35L41_TEMP_WARN_IRQ,
+ CS35L41_TEMP_ERR_IRQ,
+ CS35L41_AMP_SHORT_ERR_IRQ,
+
+ CS35L41_NUM_IRQ
+};
+
extern struct regmap_config cs35l41_regmap_i2c;
extern struct regmap_config cs35l41_regmap_spi;
int cs35l41_set_channels(struct device *dev, struct regmap *reg,
unsigned int tx_num, unsigned int *tx_slot,
unsigned int rx_num, unsigned int *rx_slot);
-int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind, int boost_cap,
- int boost_ipk);
+int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg);
+void cs35l41_configure_cs_dsp(struct device *dev, struct regmap *reg, struct cs_dsp *dsp);
+int cs35l41_set_cspl_mbox_cmd(struct device *dev, struct regmap *regmap,
+ enum cs35l41_cspl_mbox_cmd cmd);
+int cs35l41_write_fs_errata(struct device *dev, struct regmap *regmap);
+int cs35l41_init_boost(struct device *dev, struct regmap *regmap,
+ struct cs35l41_hw_cfg *hw_cfg);
+bool cs35l41_safe_reset(struct regmap *regmap, enum cs35l41_boost_type b_type);
+int cs35l41_global_enable(struct regmap *regmap, enum cs35l41_boost_type b_type, int enable);
#endif /* __CS35L41_H */
projects / linux-2.6-microblaze.git / blobdiff