__u64 flags;
};
-#define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_BEFORE 0x01
-#define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_AFTER 0x02
-#define V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR 0x03
+#define V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE 0x01
#define V4L2_HEVC_DPB_ENTRIES_NUM_MAX 16
struct v4l2_hevc_dpb_entry {
__u64 timestamp;
- __u8 rps;
+ __u8 flags;
__u8 field_pic;
__u16 pic_order_cnt[2];
__u8 padding[2];