Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be' into...

[linux-2.6-microblaze.git] / include / linux / clk-provider.h

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 677df78..46d5fc3 100644 (file)
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -348,6 +348,9 @@ void of_fixed_clk_setup(struct device_node *np);
  *     of this register, and mask of gate bits are in higher 16-bit of this
  *     register.  While setting the gate bits, higher 16-bit should also be
  *     updated to indicate changing gate bits.
+ * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
+ *     the gate register.  Setting this flag makes the register accesses big
+ *     endian.
  */
 struct clk_gate {
        struct clk_hw hw;
@@ -361,6 +364,7 @@ struct clk_gate {
 
 #define CLK_GATE_SET_TO_DISABLE                BIT(0)
 #define CLK_GATE_HIWORD_MASK           BIT(1)
+#define CLK_GATE_BIG_ENDIAN            BIT(2)
 
 extern const struct clk_ops clk_gate_ops;
 struct clk *clk_register_gate(struct device *dev, const char *name,
@@ -416,6 +420,9 @@ struct clk_div_table {
  * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
  *     except when the value read from the register is zero, the divisor is
  *     2^width of the field.
+ * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
+ *     for the divider register.  Setting this flag makes the register accesses
+ *     big endian.
  */
 struct clk_divider {
        struct clk_hw   hw;
@@ -437,6 +444,7 @@ struct clk_divider {
 #define CLK_DIVIDER_ROUND_CLOSEST      BIT(4)
 #define CLK_DIVIDER_READ_ONLY          BIT(5)
 #define CLK_DIVIDER_MAX_AT_ZERO                BIT(6)
+#define CLK_DIVIDER_BIG_ENDIAN         BIT(7)
 
 extern const struct clk_ops clk_divider_ops;
 extern const struct clk_ops clk_divider_ro_ops;
@@ -502,6 +510,9 @@ void clk_hw_unregister_divider(struct clk_hw *hw);
  *     .get_parent clk_op.
  * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
  *     frequency.
+ * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
+ *     the mux register.  Setting this flag makes the register accesses big
+ *     endian.
  */
 struct clk_mux {
        struct clk_hw   hw;
@@ -520,6 +531,7 @@ struct clk_mux {
 #define CLK_MUX_HIWORD_MASK            BIT(2)
 #define CLK_MUX_READ_ONLY              BIT(3) /* mux can't be changed */
 #define CLK_MUX_ROUND_CLOSEST          BIT(4)
+#define CLK_MUX_BIG_ENDIAN             BIT(5)
 
 extern const struct clk_ops clk_mux_ops;
 extern const struct clk_ops clk_mux_ro_ops;
@@ -603,6 +615,9 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
  *     is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
  *     is set then the numerator and denominator are both the value read
  *     plus one.
+ * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
+ *     used for the divider register.  Setting this flag makes the register
+ *     accesses big endian.
  */
 struct clk_fractional_divider {
        struct clk_hw   hw;
@@ -623,6 +638,7 @@ struct clk_fractional_divider {
 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
 
 #define CLK_FRAC_DIVIDER_ZERO_BASED            BIT(0)
+#define CLK_FRAC_DIVIDER_BIG_ENDIAN            BIT(1)
 
 extern const struct clk_ops clk_fractional_divider_ops;
 struct clk *clk_register_fractional_divider(struct device *dev,
@@ -655,6 +671,9 @@ void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
  *     leaving the parent rate unmodified.
  * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
  *     rounded to the closest integer instead of the down one.
+ * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
+ *     used for the multiplier register.  Setting this flag makes the register
+ *     accesses big endian.
  */
 struct clk_multiplier {
        struct clk_hw   hw;
@@ -669,6 +688,7 @@ struct clk_multiplier {
 
 #define CLK_MULTIPLIER_ZERO_BYPASS             BIT(0)
 #define CLK_MULTIPLIER_ROUND_CLOSEST   BIT(1)
+#define CLK_MULTIPLIER_BIG_ENDIAN              BIT(2)
 
 extern const struct clk_ops clk_multiplier_ops;
 
@@ -775,6 +795,9 @@ unsigned int __clk_get_enable_count(struct clk *clk);
 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
 unsigned long __clk_get_flags(struct clk *clk);
 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
+#define clk_hw_can_set_rate_parent(hw) \
+       (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
+
 bool clk_hw_is_prepared(const struct clk_hw *hw);
 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
 bool clk_hw_is_enabled(const struct clk_hw *hw);
@@ -973,37 +996,6 @@ static inline int of_clk_detect_critical(struct device_node *np, int index,
 }
 #endif /* CONFIG_OF */
 
-/*
- * wrap access to peripherals in accessor routines
- * for improved portability across platforms
- */
-
-#if IS_ENABLED(CONFIG_PPC)
-
-static inline u32 clk_readl(u32 __iomem *reg)
-{
-       return ioread32be(reg);
-}
-
-static inline void clk_writel(u32 val, u32 __iomem *reg)
-{
-       iowrite32be(val, reg);
-}
-
-#else  /* platform dependent I/O accessors */
-
-static inline u32 clk_readl(u32 __iomem *reg)
-{
-       return readl(reg);
-}
-
-static inline void clk_writel(u32 val, u32 __iomem *reg)
-{
-       writel(val, reg);
-}
-
-#endif /* platform dependent I/O accessors */
-
 void clk_gate_restore_context(struct clk_hw *hw);
 
 #endif /* CONFIG_COMMON_CLK */