Merge tag 'drm-next-2024-03-13' of https://gitlab.freedesktop.org/drm/kernel

[linux-2.6-microblaze.git] / include / drm / display / drm_dp.h

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 3731828..4891bd9 100644 (file)
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -718,6 +718,7 @@
 # define DP_PSR_SU_REGION_SCANLINE_CAPTURE     BIT(4) /* eDP 1.4a */
 # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS                BIT(5) /* eDP 1.4a */
 # define DP_PSR_ENABLE_PSR2                    BIT(6) /* eDP 1.4a */
+# define DP_PSR_ENABLE_SU_REGION_ET             BIT(7) /* eDP 1.5 */
 
 #define DP_ADAPTER_CTRL                            0x1a0
 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE   (1 << 0)
@@ -1080,6 +1081,7 @@
 # define STREAM_STATUS_CHANGED               (1 << 2)
 # define HDMI_LINK_STATUS_CHANGED            (1 << 3)
 # define CONNECTED_OFF_ENTRY_REQUESTED       (1 << 4)
+# define DP_TUNNELING_IRQ                    (1 << 5)
 
 #define DP_PSR_ERROR_STATUS                 0x2006  /* XXX 1.2? */
 # define DP_PSR_LINK_CRC_ERROR              (1 << 0)
@@ -1381,6 +1383,66 @@
 #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET     0x69494
 #define DP_HDCP_2_2_REG_DBG_OFFSET             0x69518
 
+/* DP-tunneling */
+#define DP_TUNNELING_OUI                               0xe0000
+#define  DP_TUNNELING_OUI_BYTES                                3
+
+#define DP_TUNNELING_DEV_ID                            0xe0003
+#define  DP_TUNNELING_DEV_ID_BYTES                     6
+
+#define DP_TUNNELING_HW_REV                            0xe0009
+#define  DP_TUNNELING_HW_REV_MAJOR_SHIFT               4
+#define  DP_TUNNELING_HW_REV_MAJOR_MASK                        (0xf << DP_TUNNELING_HW_REV_MAJOR_SHIFT)
+#define  DP_TUNNELING_HW_REV_MINOR_SHIFT               0
+#define  DP_TUNNELING_HW_REV_MINOR_MASK                        (0xf << DP_TUNNELING_HW_REV_MINOR_SHIFT)
+
+#define DP_TUNNELING_SW_REV_MAJOR                      0xe000a
+#define DP_TUNNELING_SW_REV_MINOR                      0xe000b
+
+#define DP_TUNNELING_CAPABILITIES                      0xe000d
+#define  DP_IN_BW_ALLOCATION_MODE_SUPPORT              (1 << 7)
+#define  DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT          (1 << 6)
+#define  DP_TUNNELING_SUPPORT                          (1 << 0)
+
+#define DP_IN_ADAPTER_INFO                             0xe000e
+#define  DP_IN_ADAPTER_NUMBER_BITS                     7
+#define  DP_IN_ADAPTER_NUMBER_MASK                     ((1 << DP_IN_ADAPTER_NUMBER_BITS) - 1)
+
+#define DP_USB4_DRIVER_ID                              0xe000f
+#define  DP_USB4_DRIVER_ID_BITS                                4
+#define  DP_USB4_DRIVER_ID_MASK                                ((1 << DP_USB4_DRIVER_ID_BITS) - 1)
+
+#define DP_USB4_DRIVER_BW_CAPABILITY                   0xe0020
+#define  DP_USB4_DRIVER_BW_ALLOCATION_MODE_SUPPORT     (1 << 7)
+
+#define DP_IN_ADAPTER_TUNNEL_INFORMATION               0xe0021
+#define  DP_GROUP_ID_BITS                              3
+#define  DP_GROUP_ID_MASK                              ((1 << DP_GROUP_ID_BITS) - 1)
+
+#define DP_BW_GRANULARITY                              0xe0022
+#define  DP_BW_GRANULARITY_MASK                                0x3
+
+#define DP_ESTIMATED_BW                                        0xe0023
+#define DP_ALLOCATED_BW                                        0xe0024
+
+#define DP_TUNNELING_STATUS                            0xe0025
+#define  DP_BW_ALLOCATION_CAPABILITY_CHANGED           (1 << 3)
+#define  DP_ESTIMATED_BW_CHANGED                       (1 << 2)
+#define  DP_BW_REQUEST_SUCCEEDED                       (1 << 1)
+#define  DP_BW_REQUEST_FAILED                          (1 << 0)
+
+#define DP_TUNNELING_MAX_LINK_RATE                     0xe0028
+
+#define DP_TUNNELING_MAX_LANE_COUNT                    0xe0029
+#define  DP_TUNNELING_MAX_LANE_COUNT_MASK              0x1f
+
+#define DP_DPTX_BW_ALLOCATION_MODE_CONTROL             0xe0030
+#define  DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE   (1 << 7)
+#define  DP_UNMASK_BW_ALLOCATION_IRQ                   (1 << 6)
+
+#define DP_REQUEST_BW                                  0xe0031
+#define  MAX_DP_REQUEST_BW                             255
+
 /* LTTPR: Link Training (LT)-tunable PHY Repeaters */
 #define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
 #define DP_MAX_LINK_RATE_PHY_REPEATER                      0xf0001 /* 1.4a */