TSHUT_HIGH_ACTIVE,
};
-/*
- * The system has two Temperature Sensors.
- * sensor0 is for CPU, and sensor1 is for GPU.
- */
-enum sensor_id {
- SENSOR_CPU = 0,
- SENSOR_GPU,
-};
-
/*
* The conversion table has the adc value and temperature.
* ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
#include "thermal_hwmon.h"
-/*
- * The max sensors is two in rockchip SoCs.
- * Two sensors: CPU and GPU sensor.
- */
-#define SOC_MAX_SENSORS 2
-
/**
* struct chip_tsadc_table - hold information about chip-specific differences
* @id: conversion table
/**
* struct rockchip_tsadc_chip - hold the private data of tsadc chip
- * @chn_id: array of sensor ids of chip corresponding to the channel
+ * @chn_offset: the channel offset of the first channel
* @chn_num: the channel number of tsadc chip
* @tshut_temp: the hardware-controlled shutdown temperature value
* @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
*/
struct rockchip_tsadc_chip {
/* The sensor id of chip correspond to the ADC channel */
- int chn_id[SOC_MAX_SENSORS];
+ int chn_offset;
int chn_num;
/* The hardware-controlled tshut property */
struct platform_device *pdev;
struct reset_control *reset;
- struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
+ struct rockchip_thermal_sensor *sensors;
struct clk *clk;
struct clk *pclk;
#define TSADCV2_AUTO_CON 0x04
#define TSADCV2_INT_EN 0x08
#define TSADCV2_INT_PD 0x0c
+#define TSADCV3_AUTO_SRC_CON 0x0c
+#define TSADCV3_HT_INT_EN 0x14
+#define TSADCV3_HSHUT_GPIO_INT_EN 0x18
+#define TSADCV3_HSHUT_CRU_INT_EN 0x1c
+#define TSADCV3_INT_PD 0x24
+#define TSADCV3_HSHUT_PD 0x28
#define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
#define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
#define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
+#define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04)
+#define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04)
+#define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04)
#define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
#define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
+#define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c
+#define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150
#define TSADCV2_AUTO_PERIOD 0x68
#define TSADCV2_AUTO_PERIOD_HT 0x6c
+#define TSADCV3_AUTO_PERIOD 0x154
+#define TSADCV3_AUTO_PERIOD_HT 0x158
#define TSADCV2_AUTO_EN BIT(0)
+#define TSADCV2_AUTO_EN_MASK BIT(16)
#define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
+#define TSADCV3_AUTO_SRC_EN(chn) BIT(chn)
+#define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + chn)
#define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
+#define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
#define TSADCV3_AUTO_Q_SEL_EN BIT(1)
#define TSADCV2_INT_SRC_EN(chn) BIT(chn)
+#define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
#define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
#define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
#define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
#define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
+#define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff
#define TSADCV2_DATA_MASK 0xfff
#define TSADCV3_DATA_MASK 0x3ff
+#define TSADCV4_DATA_MASK 0x1ff
#define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
#define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
#define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */
#define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
+#define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */
+#define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
#define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
#define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
#define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2)
#define RK3568_GRF_TSADC_TSEN (0x10001 << 8)
+#define RK3588_GRF0_TSADC_CON 0x0100
+
+#define RK3588_GRF0_TSADC_TRM (0xff0077 << 0)
+#define RK3588_GRF0_TSADC_SHUT_2CRU (0x30003 << 10)
+#define RK3588_GRF0_TSADC_SHUT_2GPIO (0x70007 << 12)
+
#define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
#define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
#define GRF_TSADC_VCM_EN_L (0x10001 << 7)
{TSADCV2_DATA_MASK, 125000},
};
+static const struct tsadc_table rk3588_code_table[] = {
+ {0, -40000},
+ {215, -40000},
+ {285, 25000},
+ {350, 85000},
+ {395, 125000},
+ {TSADCV4_DATA_MASK, 125000},
+};
+
static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
int temp)
{
}
}
+static void rk_tsadcv8_initialize(struct regmap *grf, void __iomem *regs,
+ enum tshut_polarity tshut_polarity)
+{
+ writel_relaxed(TSADCV6_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
+ writel_relaxed(TSADCV6_AUTO_PERIOD_HT_TIME,
+ regs + TSADCV3_AUTO_PERIOD_HT);
+ writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
+ regs + TSADCV3_HIGHT_INT_DEBOUNCE);
+ writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
+ regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
+ if (tshut_polarity == TSHUT_HIGH_ACTIVE)
+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
+ TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ regs + TSADCV2_AUTO_CON);
+ else
+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ regs + TSADCV2_AUTO_CON);
+}
+
static void rk_tsadcv2_irq_ack(void __iomem *regs)
{
u32 val;
writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
}
+static void rk_tsadcv4_irq_ack(void __iomem *regs)
+{
+ u32 val;
+
+ val = readl_relaxed(regs + TSADCV3_INT_PD);
+ writel_relaxed(val & TSADCV4_INT_PD_CLEAR_MASK, regs + TSADCV3_INT_PD);
+ val = readl_relaxed(regs + TSADCV3_HSHUT_PD);
+ writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK,
+ regs + TSADCV3_HSHUT_PD);
+}
+
static void rk_tsadcv2_control(void __iomem *regs, bool enable)
{
u32 val;
writel_relaxed(val, regs + TSADCV2_AUTO_CON);
}
+static void rk_tsadcv4_control(void __iomem *regs, bool enable)
+{
+ u32 val;
+
+ if (enable)
+ val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK;
+ else
+ val = TSADCV2_AUTO_EN_MASK;
+
+ writel_relaxed(val, regs + TSADCV2_AUTO_CON);
+}
+
static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
int chn, void __iomem *regs, int *temp)
{
return rk_tsadcv2_code_to_temp(table, val, temp);
}
+static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table,
+ int chn, void __iomem *regs, int *temp)
+{
+ u32 val;
+
+ val = readl_relaxed(regs + TSADCV3_DATA(chn));
+
+ return rk_tsadcv2_code_to_temp(table, val, temp);
+}
+
static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
int chn, void __iomem *regs, int temp)
{
return 0;
}
+static int rk_tsadcv3_alarm_temp(const struct chip_tsadc_table *table,
+ int chn, void __iomem *regs, int temp)
+{
+ u32 alarm_value;
+
+ /*
+ * In some cases, some sensors didn't need the trip points, the
+ * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
+ * in the end, ignore this case and disable the high temperature
+ * interrupt.
+ */
+ if (temp == INT_MAX) {
+ writel_relaxed(TSADCV2_INT_SRC_EN_MASK(chn),
+ regs + TSADCV3_HT_INT_EN);
+ return 0;
+ }
+ /* Make sure the value is valid */
+ alarm_value = rk_tsadcv2_temp_to_code(table, temp);
+ if (alarm_value == table->data_mask)
+ return -ERANGE;
+ writel_relaxed(alarm_value & table->data_mask,
+ regs + TSADCV3_COMP_INT(chn));
+ writel_relaxed(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn),
+ regs + TSADCV3_HT_INT_EN);
+ return 0;
+}
+
static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
int chn, void __iomem *regs, int temp)
{
return 0;
}
+static int rk_tsadcv3_tshut_temp(const struct chip_tsadc_table *table,
+ int chn, void __iomem *regs, int temp)
+{
+ u32 tshut_value;
+
+ /* Make sure the value is valid */
+ tshut_value = rk_tsadcv2_temp_to_code(table, temp);
+ if (tshut_value == table->data_mask)
+ return -ERANGE;
+
+ writel_relaxed(tshut_value, regs + TSADCV3_COMP_SHUT(chn));
+
+ /* TSHUT will be valid */
+ writel_relaxed(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn),
+ regs + TSADCV3_AUTO_SRC_CON);
+
+ return 0;
+}
+
static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
enum tshut_mode mode)
{
writel_relaxed(val, regs + TSADCV2_INT_EN);
}
+static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs,
+ enum tshut_mode mode)
+{
+ u32 val_gpio, val_cru;
+
+ if (mode == TSHUT_MODE_GPIO) {
+ val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
+ val_cru = TSADCV2_INT_SRC_EN_MASK(chn);
+ } else {
+ val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
+ val_gpio = TSADCV2_INT_SRC_EN_MASK(chn);
+ }
+ writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN);
+ writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN);
+}
+
static const struct rockchip_tsadc_chip px30_tsadc_data = {
- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
- .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
+ /* cpu, gpu */
+ .chn_offset = 0,
.chn_num = 2, /* 2 channels for tsadc */
.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
};
static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
+ /* cpu */
+ .chn_offset = 0,
.chn_num = 1, /* one channel for tsadc */
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
};
static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
+ /* cpu */
+ .chn_offset = 0,
.chn_num = 1, /* one channel for tsadc */
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
};
static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
- .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
- .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
+ /* cpu, gpu */
+ .chn_offset = 1,
.chn_num = 2, /* two channels for tsadc */
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
};
static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
+ /* cpu */
+ .chn_offset = 0,
.chn_num = 1, /* one channels for tsadc */
.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
};
static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
- .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
+ /* cpu, gpu */
+ .chn_offset = 0,
.chn_num = 2, /* two channels for tsadc */
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
};
static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
- .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
+ /* cpu, gpu */
+ .chn_offset = 0,
.chn_num = 2, /* two channels for tsadc */
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
};
static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
- .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
+ /* cpu, gpu */
+ .chn_offset = 0,
.chn_num = 2, /* two channels for tsadc */
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
};
static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
- .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
+ /* cpu, gpu */
+ .chn_offset = 0,
.chn_num = 2, /* two channels for tsadc */
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
},
};
+static const struct rockchip_tsadc_chip rk3588_tsadc_data = {
+ /* top, big_core0, big_core1, little_core, center, gpu, npu */
+ .chn_offset = 0,
+ .chn_num = 7, /* seven channels for tsadc */
+ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
+ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
+ .tshut_temp = 95000,
+ .initialize = rk_tsadcv8_initialize,
+ .irq_ack = rk_tsadcv4_irq_ack,
+ .control = rk_tsadcv4_control,
+ .get_temp = rk_tsadcv4_get_temp,
+ .set_alarm_temp = rk_tsadcv3_alarm_temp,
+ .set_tshut_temp = rk_tsadcv3_tshut_temp,
+ .set_tshut_mode = rk_tsadcv3_tshut_mode,
+ .table = {
+ .id = rk3588_code_table,
+ .length = ARRAY_SIZE(rk3588_code_table),
+ .data_mask = TSADCV4_DATA_MASK,
+ .mode = ADC_INCREMENT,
+ },
+};
+
static const struct of_device_id of_rockchip_thermal_match[] = {
{ .compatible = "rockchip,px30-tsadc",
.data = (void *)&px30_tsadc_data,
.compatible = "rockchip,rk3568-tsadc",
.data = (void *)&rk3568_tsadc_data,
},
+ {
+ .compatible = "rockchip,rk3588-tsadc",
+ .data = (void *)&rk3588_tsadc_data,
+ },
{ /* end */ },
};
MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
static int rockchip_thermal_set_trips(struct thermal_zone_device *tz, int low, int high)
{
- struct rockchip_thermal_sensor *sensor = tz->devdata;
+ struct rockchip_thermal_sensor *sensor = thermal_zone_device_priv(tz);
struct rockchip_thermal_data *thermal = sensor->thermal;
const struct rockchip_tsadc_chip *tsadc = thermal->chip;
static int rockchip_thermal_get_temp(struct thermal_zone_device *tz, int *out_temp)
{
- struct rockchip_thermal_sensor *sensor = tz->devdata;
+ struct rockchip_thermal_sensor *sensor = thermal_zone_device_priv(tz);
struct rockchip_thermal_data *thermal = sensor->thermal;
const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
int retval;
retval = tsadc->get_temp(&tsadc->table,
sensor->id, thermal->regs, out_temp);
- dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",
- sensor->id, *out_temp, retval);
-
return retval;
}
{
struct device_node *np = pdev->dev.of_node;
struct rockchip_thermal_data *thermal;
- const struct of_device_id *match;
int irq;
int i;
int error;
- match = of_match_node(of_rockchip_thermal_match, np);
- if (!match)
- return -ENXIO;
-
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return -EINVAL;
thermal->pdev = pdev;
- thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
+ thermal->chip = device_get_match_data(&pdev->dev);
if (!thermal->chip)
return -EINVAL;
+ thermal->sensors = devm_kcalloc(&pdev->dev, thermal->chip->chn_num,
+ sizeof(*thermal->sensors), GFP_KERNEL);
+ if (!thermal->sensors)
+ return -ENOMEM;
+
thermal->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
if (IS_ERR(thermal->regs))
return PTR_ERR(thermal->regs);
- thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false);
- if (IS_ERR(thermal->reset)) {
- error = PTR_ERR(thermal->reset);
- dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
- return error;
- }
-
- thermal->clk = devm_clk_get(&pdev->dev, "tsadc");
- if (IS_ERR(thermal->clk)) {
- error = PTR_ERR(thermal->clk);
- dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
- return error;
- }
+ thermal->reset = devm_reset_control_array_get_exclusive(&pdev->dev);
+ if (IS_ERR(thermal->reset))
+ return dev_err_probe(&pdev->dev, PTR_ERR(thermal->reset),
+ "failed to get tsadc reset.\n");
- thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
- if (IS_ERR(thermal->pclk)) {
- error = PTR_ERR(thermal->pclk);
- dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
- error);
- return error;
- }
+ thermal->clk = devm_clk_get_enabled(&pdev->dev, "tsadc");
+ if (IS_ERR(thermal->clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(thermal->clk),
+ "failed to get tsadc clock.\n");
- error = clk_prepare_enable(thermal->clk);
- if (error) {
- dev_err(&pdev->dev, "failed to enable converter clock: %d\n",
- error);
- return error;
- }
-
- error = clk_prepare_enable(thermal->pclk);
- if (error) {
- dev_err(&pdev->dev, "failed to enable pclk: %d\n", error);
- goto err_disable_clk;
- }
+ thermal->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
+ if (IS_ERR(thermal->pclk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(thermal->pclk),
+ "failed to get apb_pclk clock.\n");
rockchip_thermal_reset_controller(thermal->reset);
error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
- if (error) {
- dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
- error);
- goto err_disable_pclk;
- }
+ if (error)
+ return dev_err_probe(&pdev->dev, error,
+ "failed to parse device tree data\n");
thermal->chip->initialize(thermal->grf, thermal->regs,
thermal->tshut_polarity);
for (i = 0; i < thermal->chip->chn_num; i++) {
error = rockchip_thermal_register_sensor(pdev, thermal,
&thermal->sensors[i],
- thermal->chip->chn_id[i]);
- if (error) {
- dev_err(&pdev->dev,
- "failed to register sensor[%d] : error = %d\n",
- i, error);
- goto err_disable_pclk;
- }
+ thermal->chip->chn_offset + i);
+ if (error)
+ return dev_err_probe(&pdev->dev, error,
+ "failed to register sensor[%d].\n", i);
}
error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
&rockchip_thermal_alarm_irq_thread,
IRQF_ONESHOT,
"rockchip_thermal", thermal);
- if (error) {
- dev_err(&pdev->dev,
- "failed to request tsadc irq: %d\n", error);
- goto err_disable_pclk;
- }
+ if (error)
+ return dev_err_probe(&pdev->dev, error,
+ "failed to request tsadc irq.\n");
thermal->chip->control(thermal->regs, true);
for (i = 0; i < thermal->chip->chn_num; i++) {
rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
- thermal->sensors[i].tzd->tzp->no_hwmon = false;
error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd);
if (error)
dev_warn(&pdev->dev,
platform_set_drvdata(pdev, thermal);
return 0;
-
-err_disable_pclk:
- clk_disable_unprepare(thermal->pclk);
-err_disable_clk:
- clk_disable_unprepare(thermal->clk);
-
- return error;
}
static int rockchip_thermal_remove(struct platform_device *pdev)
thermal->chip->control(thermal->regs, false);
- clk_disable_unprepare(thermal->pclk);
- clk_disable_unprepare(thermal->clk);
-
return 0;
}
projects / linux-2.6-microblaze.git / blobdiff