Merge v5.14-rc3 into usb-next

[linux-2.6-microblaze.git] / drivers / spi / spi-imx.c

diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 39dc02e..4aee3db 100644 (file)
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -506,7 +506,7 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
 {
        struct spi_device *spi = msg->spi;
        u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
-       u32 testreg;
+       u32 testreg, delay;
        u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
 
        /* set Master or Slave mode */
@@ -567,6 +567,23 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
 
        writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
 
+       /*
+        * Wait until the changes in the configuration register CONFIGREG
+        * propagate into the hardware. It takes exactly one tick of the
+        * SCLK clock, but we will wait two SCLK clock just to be sure. The
+        * effect of the delay it takes for the hardware to apply changes
+        * is noticable if the SCLK clock run very slow. In such a case, if
+        * the polarity of SCLK should be inverted, the GPIO ChipSelect might
+        * be asserted before the SCLK polarity changes, which would disrupt
+        * the SPI communication as the device on the other end would consider
+        * the change of SCLK polarity as a clock tick already.
+        */
+       delay = (2 * 1000000) / spi_imx->spi_bus_clk;
+       if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
+               udelay(delay);
+       else                    /* SCLK is _very_ slow */
+               usleep_range(delay, delay + 10);
+
        return 0;
 }
 
@@ -574,7 +591,7 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
                                       struct spi_device *spi)
 {
        u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
-       u32 clk, delay;
+       u32 clk;
 
        /* Clear BL field and set the right value */
        ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
@@ -596,23 +613,6 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
 
        writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 
-       /*
-        * Wait until the changes in the configuration register CONFIGREG
-        * propagate into the hardware. It takes exactly one tick of the
-        * SCLK clock, but we will wait two SCLK clock just to be sure. The
-        * effect of the delay it takes for the hardware to apply changes
-        * is noticable if the SCLK clock run very slow. In such a case, if
-        * the polarity of SCLK should be inverted, the GPIO ChipSelect might
-        * be asserted before the SCLK polarity changes, which would disrupt
-        * the SPI communication as the device on the other end would consider
-        * the change of SCLK polarity as a clock tick already.
-        */
-       delay = (2 * 1000000) / clk;
-       if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
-               udelay(delay);
-       else                    /* SCLK is _very_ slow */
-               usleep_range(delay, delay + 10);
-
        return 0;
 }