#define SPI_FSI_BASE 0x70000
#define SPI_FSI_INIT_TIMEOUT_MS 1000
#define SPI_FSI_MAX_XFR_SIZE 2048
-#define SPI_FSI_MAX_XFR_SIZE_RESTRICTED 32
+#define SPI_FSI_MAX_XFR_SIZE_RESTRICTED 8
#define SPI_FSI_ERROR 0x0
#define SPI_FSI_COUNTER_CFG 0x1
struct fsi_spi_sequence *seq,
struct spi_transfer *transfer)
{
- bool docfg = false;
int loops;
int idx;
int rc;
u8 val = 0;
u8 len = min(transfer->len, 8U);
u8 rem = transfer->len % len;
- u64 cfg = 0ULL;
loops = transfer->len / len;
return -EINVAL;
}
- if (ctx->restricted) {
- const int eidx = rem ? 5 : 6;
-
- while (loops > 1 && idx <= eidx) {
- idx = fsi_spi_sequence_add(seq, val);
- loops--;
- docfg = true;
- }
-
- if (loops > 1) {
- dev_warn(ctx->dev, "No sequencer slots; aborting.\n");
- return -EINVAL;
- }
+ if (ctx->restricted && loops > 1) {
+ dev_warn(ctx->dev,
+ "Transfer too large; no branches permitted.\n");
+ return -EINVAL;
}
if (loops > 1) {
+ u64 cfg = SPI_FSI_COUNTER_CFG_LOOPS(loops - 1);
+
fsi_spi_sequence_add(seq, SPI_FSI_SEQUENCE_BRANCH(idx));
- docfg = true;
- }
- if (docfg) {
- cfg = SPI_FSI_COUNTER_CFG_LOOPS(loops - 1);
if (transfer->rx_buf)
cfg |= SPI_FSI_COUNTER_CFG_N2_RX |
SPI_FSI_COUNTER_CFG_N2_TX |