{
u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
- return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
+ return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB);
}
static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
ret = of_property_read_u32(np, "reg", &cs);
if (ret) {
dev_err(dev, "Couldn't determine chip select.\n");
+ of_node_put(np);
return ret;
}
if (cs >= CQSPI_MAX_CHIPSELECT) {
dev_err(dev, "Chip select %d out of range.\n", cs);
+ of_node_put(np);
return -EINVAL;
}
f_pdata->cs = cs;
ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
- if (ret)
+ if (ret) {
+ of_node_put(np);
return ret;
+ }
}
return 0;