scsi: libsas: aic94xx: hisi_sas: mvsas: pm8001: Use dev_is_expander()

[linux-2.6-microblaze.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c

diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
index d4650be..7ebd62d 100644 (file)
--- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
@@ -427,70 +427,70 @@ static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
                .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
                .msk = HGC_DQE_ECC_1B_ADDR_MSK,
                .shift = HGC_DQE_ECC_1B_ADDR_OFF,
-               .msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
+               .msg = "hgc_dqe_ecc1b_intr",
                .reg = HGC_DQE_ECC_ADDR,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
                .msk = HGC_IOST_ECC_1B_ADDR_MSK,
                .shift = HGC_IOST_ECC_1B_ADDR_OFF,
-               .msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
+               .msg = "hgc_iost_ecc1b_intr",
                .reg = HGC_IOST_ECC_ADDR,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
                .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
                .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
-               .msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n",
+               .msg = "hgc_itct_ecc1b_intr",
                .reg = HGC_ITCT_ECC_ADDR,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
                .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
                .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
-               .msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
+               .msg = "hgc_iostl_ecc1b_intr",
                .reg = HGC_LM_DFX_STATUS2,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
                .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
                .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
-               .msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
+               .msg = "hgc_itctl_ecc1b_intr",
                .reg = HGC_LM_DFX_STATUS2,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
                .msk = HGC_CQE_ECC_1B_ADDR_MSK,
                .shift = HGC_CQE_ECC_1B_ADDR_OFF,
-               .msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
+               .msg = "hgc_cqe_ecc1b_intr",
                .reg = HGC_CQE_ECC_ADDR,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
                .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
                .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
-               .msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
+               .msg = "rxm_mem0_ecc1b_intr",
                .reg = HGC_RXM_DFX_STATUS14,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
                .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
                .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
-               .msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
+               .msg = "rxm_mem1_ecc1b_intr",
                .reg = HGC_RXM_DFX_STATUS14,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
                .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
                .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
-               .msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
+               .msg = "rxm_mem2_ecc1b_intr",
                .reg = HGC_RXM_DFX_STATUS14,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
                .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
                .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
-               .msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
+               .msg = "rxm_mem3_ecc1b_intr",
                .reg = HGC_RXM_DFX_STATUS15,
        },
 };
@@ -500,70 +500,70 @@ static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
                .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
                .msk = HGC_DQE_ECC_MB_ADDR_MSK,
                .shift = HGC_DQE_ECC_MB_ADDR_OFF,
-               .msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
+               .msg = "hgc_dqe_eccbad_intr",
                .reg = HGC_DQE_ECC_ADDR,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
                .msk = HGC_IOST_ECC_MB_ADDR_MSK,
                .shift = HGC_IOST_ECC_MB_ADDR_OFF,
-               .msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
+               .msg = "hgc_iost_eccbad_intr",
                .reg = HGC_IOST_ECC_ADDR,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
                .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
                .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
-               .msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
+               .msg = "hgc_itct_eccbad_intr",
                .reg = HGC_ITCT_ECC_ADDR,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
                .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
                .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
-               .msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
+               .msg = "hgc_iostl_eccbad_intr",
                .reg = HGC_LM_DFX_STATUS2,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
                .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
                .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
-               .msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
+               .msg = "hgc_itctl_eccbad_intr",
                .reg = HGC_LM_DFX_STATUS2,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
                .msk = HGC_CQE_ECC_MB_ADDR_MSK,
                .shift = HGC_CQE_ECC_MB_ADDR_OFF,
-               .msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
+               .msg = "hgc_cqe_eccbad_intr",
                .reg = HGC_CQE_ECC_ADDR,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
                .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
                .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
-               .msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n",
+               .msg = "rxm_mem0_eccbad_intr",
                .reg = HGC_RXM_DFX_STATUS14,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
                .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
                .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
-               .msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n",
+               .msg = "rxm_mem1_eccbad_intr",
                .reg = HGC_RXM_DFX_STATUS14,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
                .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
                .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
-               .msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n",
+               .msg = "rxm_mem2_eccbad_intr",
                .reg = HGC_RXM_DFX_STATUS14,
        },
        {
                .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
                .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
                .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
-               .msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n",
+               .msg = "rxm_mem3_eccbad_intr",
                .reg = HGC_RXM_DFX_STATUS15,
        },
 };
@@ -949,7 +949,7 @@ static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
                break;
        case SAS_SATA_DEV:
        case SAS_SATA_PENDING:
-               if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
+               if (parent_dev && dev_is_expander(parent_dev->dev_type))
                        qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
                else
                        qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
@@ -2531,7 +2531,7 @@ static void prep_ata_v2_hw(struct hisi_hba *hisi_hba,
        /* create header */
        /* dw0 */
        dw0 = port->id << CMD_HDR_PORT_OFF;
-       if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
+       if (parent_dev && dev_is_expander(parent_dev->dev_type))
                dw0 |= 3 << CMD_HDR_CMD_OFF;
        else
                dw0 |= 4 << CMD_HDR_CMD_OFF;
@@ -2978,7 +2978,8 @@ one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
                        val = hisi_sas_read32(hisi_hba, ecc_error->reg);
                        val &= ecc_error->msk;
                        val >>= ecc_error->shift;
-                       dev_warn(dev, ecc_error->msg, val);
+                       dev_warn(dev, "%s found: mem addr is 0x%08X\n",
+                                ecc_error->msg, val);
                }
        }
 }
@@ -2997,7 +2998,8 @@ static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
                        val = hisi_sas_read32(hisi_hba, ecc_error->reg);
                        val &= ecc_error->msk;
                        val >>= ecc_error->shift;
-                       dev_err(dev, ecc_error->msg, irq_value, val);
+                       dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
+                               ecc_error->msg, irq_value, val);
                        queue_work(hisi_hba->wq, &hisi_hba->rst_work);
                }
        }