Merge tag 'mac80211-next-for-net-next-2020-02-14' of git://git.kernel.org/pub/scm...

[linux-2.6-microblaze.git] / drivers / pwm / pwm-mxs.c

diff --git a/drivers/pwm/pwm-mxs.c b/drivers/pwm/pwm-mxs.c
index b14376b..f2e57fc 100644 (file)
--- a/drivers/pwm/pwm-mxs.c
+++ b/drivers/pwm/pwm-mxs.c
@@ -25,12 +25,16 @@
 #define  PERIOD_PERIOD(p)      ((p) & 0xffff)
 #define  PERIOD_PERIOD_MAX     0x10000
 #define  PERIOD_ACTIVE_HIGH    (3 << 16)
+#define  PERIOD_ACTIVE_LOW     (2 << 16)
+#define  PERIOD_INACTIVE_HIGH  (3 << 18)
 #define  PERIOD_INACTIVE_LOW   (2 << 18)
+#define  PERIOD_POLARITY_NORMAL        (PERIOD_ACTIVE_HIGH | PERIOD_INACTIVE_LOW)
+#define  PERIOD_POLARITY_INVERSE       (PERIOD_ACTIVE_LOW | PERIOD_INACTIVE_HIGH)
 #define  PERIOD_CDIV(div)      (((div) & 0x7) << 20)
 #define  PERIOD_CDIV_MAX       8
 
-static const unsigned int cdiv[PERIOD_CDIV_MAX] = {
-       1, 2, 4, 8, 16, 64, 256, 1024
+static const u8 cdiv_shift[PERIOD_CDIV_MAX] = {
+       0, 1, 2, 3, 4, 6, 8, 10
 };
 
 struct mxs_pwm_chip {
@@ -41,19 +45,34 @@ struct mxs_pwm_chip {
 
 #define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip)
 
-static int mxs_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
-                         int duty_ns, int period_ns)
+static int mxs_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+                        const struct pwm_state *state)
 {
        struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
        int ret, div = 0;
        unsigned int period_cycles, duty_cycles;
        unsigned long rate;
        unsigned long long c;
+       unsigned int pol_bits;
+
+       /*
+        * If the PWM channel is disabled, make sure to turn on the
+        * clock before calling clk_get_rate() and writing to the
+        * registers. Otherwise, just keep it enabled.
+        */
+       if (!pwm_is_enabled(pwm)) {
+               ret = clk_prepare_enable(mxs->clk);
+               if (ret)
+                       return ret;
+       }
+
+       if (!state->enabled && pwm_is_enabled(pwm))
+               writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);
 
        rate = clk_get_rate(mxs->clk);
        while (1) {
-               c = rate / cdiv[div];
-               c = c * period_ns;
+               c = rate >> cdiv_shift[div];
+               c = c * state->period;
                do_div(c, 1000000000);
                if (c < PERIOD_PERIOD_MAX)
                        break;
@@ -63,62 +82,40 @@ static int mxs_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
        }
 
        period_cycles = c;
-       c *= duty_ns;
-       do_div(c, period_ns);
+       c *= state->duty_cycle;
+       do_div(c, state->period);
        duty_cycles = c;
 
        /*
-        * If the PWM channel is disabled, make sure to turn on the clock
-        * before writing the register. Otherwise, keep it enabled.
+        * The data sheet the says registers must be written to in
+        * this order (ACTIVEn, then PERIODn). Also, the new settings
+        * only take effect at the beginning of a new period, avoiding
+        * glitches.
         */
-       if (!pwm_is_enabled(pwm)) {
-               ret = clk_prepare_enable(mxs->clk);
-               if (ret)
-                       return ret;
-       }
 
+       pol_bits = state->polarity == PWM_POLARITY_NORMAL ?
+               PERIOD_POLARITY_NORMAL : PERIOD_POLARITY_INVERSE;
        writel(duty_cycles << 16,
-                       mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
-       writel(PERIOD_PERIOD(period_cycles) | PERIOD_ACTIVE_HIGH |
-              PERIOD_INACTIVE_LOW | PERIOD_CDIV(div),
-                       mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);
-
-       /*
-        * If the PWM is not enabled, turn the clock off again to save power.
-        */
-       if (!pwm_is_enabled(pwm))
+              mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
+       writel(PERIOD_PERIOD(period_cycles) | pol_bits | PERIOD_CDIV(div),
+              mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);
+
+       if (state->enabled) {
+               if (!pwm_is_enabled(pwm)) {
+                       /*
+                        * The clock was enabled above. Just enable
+                        * the channel in the control register.
+                        */
+                       writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
+               }
+       } else {
                clk_disable_unprepare(mxs->clk);
-
-       return 0;
-}
-
-static int mxs_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
-{
-       struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
-       int ret;
-
-       ret = clk_prepare_enable(mxs->clk);
-       if (ret)
-               return ret;
-
-       writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
-
+       }
        return 0;
 }
 
-static void mxs_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
-{
-       struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
-
-       writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);
-
-       clk_disable_unprepare(mxs->clk);
-}
-
 static const struct pwm_ops mxs_pwm_ops = {
-       .config = mxs_pwm_config,
-       .enable = mxs_pwm_enable,
-       .disable = mxs_pwm_disable,
+       .apply = mxs_pwm_apply,
        .owner = THIS_MODULE,
 };
 
@@ -142,6 +139,8 @@ static int mxs_pwm_probe(struct platform_device *pdev)
 
        mxs->chip.dev = &pdev->dev;
        mxs->chip.ops = &mxs_pwm_ops;
+       mxs->chip.of_xlate = of_pwm_xlate_with_flags;
+       mxs->chip.of_pwm_n_cells = 3;
        mxs->chip.base = -1;
 
        ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm);