pwm: rcar: Convert to devm_platform_ioremap_resource()

[linux-2.6-microblaze.git] / drivers / pwm / pwm-jz4740.c

diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c
index 3cd5c05..00c642f 100644 (file)
--- a/drivers/pwm/pwm-jz4740.c
+++ b/drivers/pwm/pwm-jz4740.c
@@ -6,7 +6,6 @@
  * Limitations:
  * - The .apply callback doesn't complete the currently running period before
  *   reconfiguring the hardware.
- * - Each period starts with the inactive part.
  */
 
 #include <linux/clk.h>
@@ -21,7 +20,9 @@
 #include <linux/pwm.h>
 #include <linux/regmap.h>
 
-#define NUM_PWM 8
+struct soc_info {
+       unsigned int num_pwms;
+};
 
 struct jz4740_pwm_chip {
        struct pwm_chip chip;
@@ -37,7 +38,7 @@ static bool jz4740_pwm_can_use_chn(struct jz4740_pwm_chip *jz,
                                   unsigned int channel)
 {
        /* Enable all TCU channels for PWM use by default except channels 0/1 */
-       u32 pwm_channels_mask = GENMASK(NUM_PWM - 1, 2);
+       u32 pwm_channels_mask = GENMASK(jz->chip.npwm - 1, 2);
 
        device_property_read_u32(jz->chip.dev->parent,
                                 "ingenic,pwm-channels-mask",
@@ -59,12 +60,9 @@ static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
        snprintf(name, sizeof(name), "timer%u", pwm->hwpwm);
 
        clk = clk_get(chip->dev, name);
-       if (IS_ERR(clk)) {
-               if (PTR_ERR(clk) != -EPROBE_DEFER)
-                       dev_err(chip->dev, "Failed to get clock: %pe", clk);
-
-               return PTR_ERR(clk);
-       }
+       if (IS_ERR(clk))
+               return dev_err_probe(chip->dev, PTR_ERR(clk),
+                                    "Failed to get clock\n");
 
        err = clk_prepare_enable(clk);
        if (err < 0) {
@@ -158,12 +156,12 @@ static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
        /* Calculate period value */
        tmp = (unsigned long long)rate * state->period;
        do_div(tmp, NSEC_PER_SEC);
-       period = (unsigned long)tmp;
+       period = tmp;
 
        /* Calculate duty value */
-       tmp = (unsigned long long)period * state->duty_cycle;
-       do_div(tmp, state->period);
-       duty = period - tmp;
+       tmp = (unsigned long long)rate * state->duty_cycle;
+       do_div(tmp, NSEC_PER_SEC);
+       duty = tmp;
 
        if (duty >= period)
                duty = period - 1;
@@ -189,18 +187,26 @@ static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
        regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
                           TCU_TCSR_PWM_SD, TCU_TCSR_PWM_SD);
 
-       /* Set polarity */
-       switch (state->polarity) {
-       case PWM_POLARITY_NORMAL:
+       /*
+        * Set polarity.
+        *
+        * The PWM starts in inactive state until the internal timer reaches the
+        * duty value, then becomes active until the timer reaches the period
+        * value. In theory, we should then use (period - duty) as the real duty
+        * value, as a high duty value would otherwise result in the PWM pin
+        * being inactive most of the time.
+        *
+        * Here, we don't do that, and instead invert the polarity of the PWM
+        * when it is active. This trick makes the PWM start with its active
+        * state instead of its inactive state.
+        */
+       if ((state->polarity == PWM_POLARITY_NORMAL) ^ state->enabled)
                regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
                                   TCU_TCSR_PWM_INITL_HIGH, 0);
-               break;
-       case PWM_POLARITY_INVERSED:
+       else
                regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
                                   TCU_TCSR_PWM_INITL_HIGH,
                                   TCU_TCSR_PWM_INITL_HIGH);
-               break;
-       }
 
        if (state->enabled)
                jz4740_pwm_enable(chip, pwm);
@@ -219,6 +225,11 @@ static int jz4740_pwm_probe(struct platform_device *pdev)
 {
        struct device *dev = &pdev->dev;
        struct jz4740_pwm_chip *jz4740;
+       const struct soc_info *info;
+
+       info = device_get_match_data(dev);
+       if (!info)
+               return -EINVAL;
 
        jz4740 = devm_kzalloc(dev, sizeof(*jz4740), GFP_KERNEL);
        if (!jz4740)
@@ -232,7 +243,7 @@ static int jz4740_pwm_probe(struct platform_device *pdev)
 
        jz4740->chip.dev = dev;
        jz4740->chip.ops = &jz4740_pwm_ops;
-       jz4740->chip.npwm = NUM_PWM;
+       jz4740->chip.npwm = info->num_pwms;
        jz4740->chip.base = -1;
        jz4740->chip.of_xlate = of_pwm_xlate_with_flags;
        jz4740->chip.of_pwm_n_cells = 3;
@@ -249,9 +260,18 @@ static int jz4740_pwm_remove(struct platform_device *pdev)
        return pwmchip_remove(&jz4740->chip);
 }
 
+static const struct soc_info __maybe_unused jz4740_soc_info = {
+       .num_pwms = 8,
+};
+
+static const struct soc_info __maybe_unused jz4725b_soc_info = {
+       .num_pwms = 6,
+};
+
 #ifdef CONFIG_OF
 static const struct of_device_id jz4740_pwm_dt_ids[] = {
-       { .compatible = "ingenic,jz4740-pwm", },
+       { .compatible = "ingenic,jz4740-pwm", .data = &jz4740_soc_info },
+       { .compatible = "ingenic,jz4725b-pwm", .data = &jz4725b_soc_info },
        {},
 };
 MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids);