Merge tag 'linux-kselftest-fixes-5.11-rc1' of git://git.kernel.org/pub/scm/linux...

[linux-2.6-microblaze.git] / drivers / pinctrl / pinctrl-amd.c

diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 9a760f5..899c16c 100644 (file)
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -156,7 +156,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
                        pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
                        pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
                } else if (debounce < 250000) {
-                       time = debounce / 15600;
+                       time = debounce / 15625;
                        pin_reg |= time & DB_TMR_OUT_MASK;
                        pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
                        pin_reg |= BIT(DB_TMR_LARGE_OFF);
@@ -166,14 +166,14 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
                        pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
                        pin_reg |= BIT(DB_TMR_LARGE_OFF);
                } else {
-                       pin_reg &= ~DB_CNTRl_MASK;
+                       pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
                        ret = -EINVAL;
                }
        } else {
                pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
                pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
                pin_reg &= ~DB_TMR_OUT_MASK;
-               pin_reg &= ~DB_CNTRl_MASK;
+               pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
        }
        writel(pin_reg, gpio_dev->base + offset * 4);
        raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
@@ -429,7 +429,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
                pin_reg &= ~BIT(LEVEL_TRIG_OFF);
                pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
                pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
-               pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
                irq_set_handler_locked(d, handle_edge_irq);
                break;
 
@@ -437,7 +436,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
                pin_reg &= ~BIT(LEVEL_TRIG_OFF);
                pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
                pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
-               pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
                irq_set_handler_locked(d, handle_edge_irq);
                break;
 
@@ -445,7 +443,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
                pin_reg &= ~BIT(LEVEL_TRIG_OFF);
                pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
                pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
-               pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
                irq_set_handler_locked(d, handle_edge_irq);
                break;
 
@@ -453,8 +450,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
                pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
                pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
                pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
-               pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
-               pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
                irq_set_handler_locked(d, handle_level_irq);
                break;
 
@@ -462,8 +457,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
                pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
                pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
                pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
-               pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
-               pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
                irq_set_handler_locked(d, handle_level_irq);
                break;