perf: RISC-V: Introduce Andes PMU to support perf event sampling

[linux-2.6-microblaze.git] / drivers / perf / Kconfig

diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index ec6e0d9..564e813 100644 (file)
--- a/drivers/perf/Kconfig
+++ b/drivers/perf/Kconfig
@@ -86,6 +86,20 @@ config RISCV_PMU_SBI
          full perf feature support i.e. counter overflow, privilege mode
          filtering, counter configuration.
 
+config ANDES_CUSTOM_PMU
+       bool "Andes custom PMU support"
+       depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI
+       default y
+       help
+         The Andes cores implement the PMU overflow extension very
+         similar to the standard Sscofpmf and Smcntrpmf extension.
+
+         This will patch the overflow and pending CSRs and handle the
+         non-standard behaviour via the regular SBI PMU driver and
+         interface.
+
+         If you don't know what to do here, say "Y".
+
 config ARM_PMU_ACPI
        depends on ARM_PMU && ACPI
        def_bool y