Merge branch 'pci/printk'

[linux-2.6-microblaze.git] / drivers / pci / quirks.c

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 98c9c47..b9489b3 100644 (file)
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -159,8 +159,7 @@ static int __init pci_apply_final_quirks(void)
        u8 tmp;
 
        if (pci_cache_line_size)
-               printk(KERN_DEBUG "PCI: CLS %u bytes\n",
-                      pci_cache_line_size << 2);
+               pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
 
        pci_apply_fixup_final_quirks = true;
        for_each_pci_dev(dev) {
@@ -177,16 +176,16 @@ static int __init pci_apply_final_quirks(void)
                        if (!tmp || cls == tmp)
                                continue;
 
-                       printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
-                              cls << 2, tmp << 2,
-                              pci_dfl_cache_line_size << 2);
+                       pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
+                                cls << 2, tmp << 2,
+                                pci_dfl_cache_line_size << 2);
                        pci_cache_line_size = pci_dfl_cache_line_size;
                }
        }
 
        if (!pci_cache_line_size) {
-               printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
-                      cls << 2, pci_dfl_cache_line_size << 2);
+               pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
+                       pci_dfl_cache_line_size << 2);
                pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
        }
 
@@ -2613,7 +2612,7 @@ static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
        pci_read_config_dword(dev, 0x74, &cfg);
 
        if (cfg & ((1 << 2) | (1 << 15))) {
-               printk(KERN_INFO "Rewriting IRQ routing register on MCP55\n");
+               pr_info("Rewriting IRQ routing register on MCP55\n");
                cfg &= ~((1 << 2) | (1 << 15));
                pci_write_config_dword(dev, 0x74, cfg);
        }
@@ -3425,6 +3424,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
 
 /*
  * Root port on some Cavium CN8xxx chips do not successfully complete a bus
@@ -4920,6 +4920,7 @@ static void quirk_no_ats(struct pci_dev *pdev)
 
 /* AMD Stoney platform GPU */
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_no_ats);
 #endif /* CONFIG_PCI_ATS */
 
 /* Freescale PCIe doesn't support MSI in RC mode */