power: supply: core: Fix power_supply_init_attrs() stub

[linux-2.6-microblaze.git] / drivers / pci / pci.c

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 101af94..d8f11a0 100644 (file)
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1279,6 +1279,9 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
        if (delay > PCI_RESET_WAIT)
                pci_info(dev, "ready %dms after %s\n", delay - 1,
                         reset_type);
+       else
+               pci_dbg(dev, "ready %dms after %s\n", delay - 1,
+                       reset_type);
 
        return 0;
 }
@@ -1395,6 +1398,9 @@ static int pci_set_full_power_state(struct pci_dev *dev)
                pci_restore_bars(dev);
        }
 
+       if (dev->bus->self)
+               pcie_aspm_pm_state_change(dev->bus->self);
+
        return 0;
 }
 
@@ -1489,6 +1495,9 @@ static int pci_set_low_power_state(struct pci_dev *dev, pci_power_t state)
                                     pci_power_name(dev->current_state),
                                     pci_power_name(state));
 
+       if (dev->bus->self)
+               pcie_aspm_pm_state_change(dev->bus->self);
+
        return 0;
 }
 
@@ -6286,6 +6295,41 @@ int pcie_set_mps(struct pci_dev *dev, int mps)
 }
 EXPORT_SYMBOL(pcie_set_mps);
 
+static enum pci_bus_speed to_pcie_link_speed(u16 lnksta)
+{
+       return pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta)];
+}
+
+int pcie_link_speed_mbps(struct pci_dev *pdev)
+{
+       u16 lnksta;
+       int err;
+
+       err = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta);
+       if (err)
+               return err;
+
+       switch (to_pcie_link_speed(lnksta)) {
+       case PCIE_SPEED_2_5GT:
+               return 2500;
+       case PCIE_SPEED_5_0GT:
+               return 5000;
+       case PCIE_SPEED_8_0GT:
+               return 8000;
+       case PCIE_SPEED_16_0GT:
+               return 16000;
+       case PCIE_SPEED_32_0GT:
+               return 32000;
+       case PCIE_SPEED_64_0GT:
+               return 64000;
+       default:
+               break;
+       }
+
+       return -EINVAL;
+}
+EXPORT_SYMBOL(pcie_link_speed_mbps);
+
 /**
  * pcie_bandwidth_available - determine minimum link settings of a PCIe
  *                           device and its bandwidth limitation
@@ -6319,8 +6363,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
        while (dev) {
                pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
 
-               next_speed = pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS,
-                                                      lnksta)];
+               next_speed = to_pcie_link_speed(lnksta);
                next_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
 
                next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);