* @reg_base: IO Mapped Register Base
* @irq: Interrupt number
* @msi_pages: MSI pages
- * @root_busno: Root Bus number
* @dev: Device pointer
* @msi_domain: MSI IRQ domain pointer
* @leg_domain: Legacy IRQ domain pointer
void __iomem *reg_base;
u32 irq;
unsigned long msi_pages;
- u8 root_busno;
struct device *dev;
struct irq_domain *msi_domain;
struct irq_domain *leg_domain;
struct xilinx_pcie_port *port = bus->sysdata;
/* Check if link is up when trying to access downstream ports */
- if (bus->number != port->root_busno)
+ if (!pci_is_root_bus(bus)) {
if (!xilinx_pcie_link_up(port))
return false;
-
- /* Only one device down on each root port */
- if (bus->number == port->root_busno && devfn > 0)
+ } else if (devfn > 0) {
+ /* Only one device down on each root port */
return false;
-
+ }
return true;
}
return err;
}
- err = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
- &bridge->dma_ranges, NULL);
- if (err) {
- dev_err(dev, "Getting bridge resources failed\n");
- return err;
- }
-
- bridge->dev.parent = dev;
bridge->sysdata = port;
- bridge->busnr = 0;
bridge->ops = &xilinx_pcie_ops;
- bridge->map_irq = of_irq_parse_and_map_pci;
- bridge->swizzle_irq = pci_common_swizzle;
#ifdef CONFIG_PCI_MSI
xilinx_pcie_msi_chip.dev = dev;