Merge tag 'devicetree-fixes-for-5.17-1' of git://git.kernel.org/pub/scm/linux/kernel...

[linux-2.6-microblaze.git] / drivers / pci / controller / pcie-mt7621.c

diff --git a/drivers/pci/controller/pcie-mt7621.c b/drivers/pci/controller/pcie-mt7621.c
index b60dfb4..3824862 100644 (file)
--- a/drivers/pci/controller/pcie-mt7621.c
+++ b/drivers/pci/controller/pcie-mt7621.c
@@ -93,8 +93,8 @@ struct mt7621_pcie_port {
  * reset lines are inverted.
  */
 struct mt7621_pcie {
-       void __iomem *base;
        struct device *dev;
+       void __iomem *base;
        struct list_head ports;
        bool resets_inverted;
 };
@@ -129,7 +129,7 @@ static inline void pcie_port_write(struct mt7621_pcie_port *port,
        writel_relaxed(val, port->base + reg);
 }
 
-static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
+static inline u32 mt7621_pcie_get_cfgaddr(unsigned int bus, unsigned int slot,
                                         unsigned int func, unsigned int where)
 {
        return (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |
@@ -140,7 +140,7 @@ static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
                                         unsigned int devfn, int where)
 {
        struct mt7621_pcie *pcie = bus->sysdata;
-       u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+       u32 address = mt7621_pcie_get_cfgaddr(bus->number, PCI_SLOT(devfn),
                                             PCI_FUNC(devfn), where);
 
        writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
@@ -148,7 +148,7 @@ static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
        return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
 }
 
-struct pci_ops mt7621_pci_ops = {
+static struct pci_ops mt7621_pcie_ops = {
        .map_bus        = mt7621_pcie_map_bus,
        .read           = pci_generic_config_read,
        .write          = pci_generic_config_write,
@@ -156,7 +156,7 @@ struct pci_ops mt7621_pci_ops = {
 
 static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
 {
-       u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
+       u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);
 
        pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
        return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
@@ -165,7 +165,7 @@ static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
 static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
                         u32 reg, u32 val)
 {
-       u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
+       u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);
 
        pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
        pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
@@ -208,37 +208,6 @@ static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
                reset_control_assert(port->pcie_rst);
 }
 
-static int setup_cm_memory_region(struct pci_host_bridge *host)
-{
-       struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
-       struct device *dev = pcie->dev;
-       struct resource_entry *entry;
-       resource_size_t mask;
-
-       entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
-       if (!entry) {
-               dev_err(dev, "cannot get memory resource\n");
-               return -EINVAL;
-       }
-
-       if (mips_cps_numiocu(0)) {
-               /*
-                * FIXME: hardware doesn't accept mask values with 1s after
-                * 0s (e.g. 0xffef), so it would be great to warn if that's
-                * about to happen
-                */
-               mask = ~(entry->res->end - entry->res->start);
-
-               write_gcr_reg1_base(entry->res->start);
-               write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
-               dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
-                        (unsigned long long)read_gcr_reg1_base(),
-                        (unsigned long long)read_gcr_reg1_mask());
-       }
-
-       return 0;
-}
-
 static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
                                  struct device_node *node,
                                  int slot)
@@ -505,16 +474,16 @@ static int mt7621_pcie_register_host(struct pci_host_bridge *host)
 {
        struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
 
-       host->ops = &mt7621_pci_ops;
+       host->ops = &mt7621_pcie_ops;
        host->sysdata = pcie;
        return pci_host_probe(host);
 }
 
-static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
+static const struct soc_device_attribute mt7621_pcie_quirks_match[] = {
        { .soc_id = "mt7621", .revision = "E2" }
 };
 
-static int mt7621_pci_probe(struct platform_device *pdev)
+static int mt7621_pcie_probe(struct platform_device *pdev)
 {
        struct device *dev = &pdev->dev;
        const struct soc_device_attribute *attr;
@@ -535,7 +504,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
        platform_set_drvdata(pdev, pcie);
        INIT_LIST_HEAD(&pcie->ports);
 
-       attr = soc_device_match(mt7621_pci_quirks_match);
+       attr = soc_device_match(mt7621_pcie_quirks_match);
        if (attr)
                pcie->resets_inverted = true;
 
@@ -557,12 +526,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
                goto remove_resets;
        }
 
-       err = setup_cm_memory_region(bridge);
-       if (err) {
-               dev_err(dev, "error setting up iocu mem regions\n");
-               goto remove_resets;
-       }
-
        return mt7621_pcie_register_host(bridge);
 
 remove_resets:
@@ -572,7 +535,7 @@ remove_resets:
        return err;
 }
 
-static int mt7621_pci_remove(struct platform_device *pdev)
+static int mt7621_pcie_remove(struct platform_device *pdev)
 {
        struct mt7621_pcie *pcie = platform_get_drvdata(pdev);
        struct mt7621_pcie_port *port;
@@ -583,18 +546,20 @@ static int mt7621_pci_remove(struct platform_device *pdev)
        return 0;
 }
 
-static const struct of_device_id mt7621_pci_ids[] = {
+static const struct of_device_id mt7621_pcie_ids[] = {
        { .compatible = "mediatek,mt7621-pci" },
        {},
 };
-MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
+MODULE_DEVICE_TABLE(of, mt7621_pcie_ids);
 
-static struct platform_driver mt7621_pci_driver = {
-       .probe = mt7621_pci_probe,
-       .remove = mt7621_pci_remove,
+static struct platform_driver mt7621_pcie_driver = {
+       .probe = mt7621_pcie_probe,
+       .remove = mt7621_pcie_remove,
        .driver = {
                .name = "mt7621-pci",
-               .of_match_table = of_match_ptr(mt7621_pci_ids),
+               .of_match_table = of_match_ptr(mt7621_pcie_ids),
        },
 };
-builtin_platform_driver(mt7621_pci_driver);
+builtin_platform_driver(mt7621_pcie_driver);
+
+MODULE_LICENSE("GPL v2");