PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code

[linux-2.6-microblaze.git] / drivers / pci / controller / dwc / pci-dra7xx.c

diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
index dc38772..a4aabc8 100644 (file)
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -73,8 +73,6 @@
 #define        LINK_UP                                         BIT(16)
 #define        DRA7XX_CPU_TO_BUS_ADDR                          0x0FFFFFFF
 
-#define EXP_CAP_ID_OFFSET                              0x70
-
 #define        PCIECTRL_TI_CONF_INTX_ASSERT                    0x0124
 #define        PCIECTRL_TI_CONF_INTX_DEASSERT                  0x0128
 
@@ -91,7 +89,6 @@ struct dra7xx_pcie {
        void __iomem            *base;          /* DT ti_conf */
        int                     phy_count;      /* DT phy-names count */
        struct phy              **phy;
-       int                     link_gen;
        struct irq_domain       *irq_domain;
        enum dw_pcie_device_mode mode;
 };
@@ -142,33 +139,12 @@ static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
        struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
        struct device *dev = pci->dev;
        u32 reg;
-       u32 exp_cap_off = EXP_CAP_ID_OFFSET;
 
        if (dw_pcie_link_up(pci)) {
                dev_err(dev, "link is already up\n");
                return 0;
        }
 
-       if (dra7xx->link_gen == 1) {
-               dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
-                            4, &reg);
-               if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
-                       reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
-                       reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
-                       dw_pcie_write(pci->dbi_base + exp_cap_off +
-                                     PCI_EXP_LNKCAP, 4, reg);
-               }
-
-               dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
-                            2, &reg);
-               if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
-                       reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
-                       reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
-                       dw_pcie_write(pci->dbi_base + exp_cap_off +
-                                     PCI_EXP_LNKCTL2, 2, reg);
-               }
-       }
-
        reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
        reg |= LTSSM_EN;
        dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
@@ -490,7 +466,9 @@ static struct irq_chip dra7xx_pci_msi_bottom_irq_chip = {
 static int dra7xx_pcie_msi_host_init(struct pcie_port *pp)
 {
        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+       struct device *dev = pci->dev;
        u32 ctrl, num_ctrls;
+       int ret;
 
        pp->msi_irq_chip = &dra7xx_pci_msi_bottom_irq_chip;
 
@@ -506,7 +484,21 @@ static int dra7xx_pcie_msi_host_init(struct pcie_port *pp)
                                    ~0);
        }
 
-       return dw_pcie_allocate_domains(pp);
+       ret = dw_pcie_allocate_domains(pp);
+       if (ret)
+               return ret;
+
+       pp->msi_data = dma_map_single_attrs(dev, &pp->msi_msg,
+                                          sizeof(pp->msi_msg),
+                                          DMA_FROM_DEVICE,
+                                          DMA_ATTR_SKIP_CPU_SYNC);
+       ret = dma_mapping_error(dev, pp->msi_data);
+       if (ret) {
+               dev_err(dev, "Failed to map MSI data\n");
+               pp->msi_data = 0;
+               dw_pcie_free_msi(pp);
+       }
+       return ret;
 }
 
 static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
@@ -586,7 +578,6 @@ static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
 {
        int ret;
        struct dw_pcie_ep *ep;
-       struct resource *res;
        struct device *dev = &pdev->dev;
        struct dw_pcie *pci = dra7xx->pci;
 
@@ -602,13 +593,6 @@ static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
        if (IS_ERR(pci->dbi_base2))
                return PTR_ERR(pci->dbi_base2);
 
-       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
-       if (!res)
-               return -EINVAL;
-
-       ep->phys_base = res->start;
-       ep->addr_size = resource_size(res);
-
        ret = dw_pcie_ep_init(ep);
        if (ret) {
                dev_err(dev, "failed to initialize endpoint\n");
@@ -937,10 +921,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
        reg &= ~LTSSM_EN;
        dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
 
-       dra7xx->link_gen = of_pci_get_max_link_speed(np);
-       if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
-               dra7xx->link_gen = 2;
-
        switch (mode) {
        case DW_PCIE_RC_TYPE:
                if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {